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Applied Physics Letters

High speed logic operations of all refractory Josephson integrated circuits

S. Kosaka, Akira Shoji, Masahiro Aoyagi, Fujitoshi Shinoki, Hiroshi Nakagawa, S. Takada, Hisao Hayakawa

Published Jul 15, 1983• 16 citations
Publisher

Abstract

A chain circuit of four-junction logic gates consisting of all refractory junctions with niobium nitride (NbN)-niobium (Nb) double-layered electrodes has been fabricated with a 2.5-μm minimum feature. A reactive ion etching technique has been used for patterning every layer such as junction electrodes, molybdenum resistors, and insulation layers. The minimum logic delay of 18 ps/gate has been obtained in the experimental circuit.

DOI
10.1063/1.94259

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Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE•Jul 7, 1997•2 citations
A chain circuit of four-junction logic gates consisting of all refractory junctions with niobium nitride (NbN)-niobium (Nb) double-layered electrodes has been fabricated with a 2.5-μm minimum feature. A reactive ion etching technique has been used for patterning every layer such as junction electrodes, molybdenum resistors, and insulation layers. The minimum logic delay of 18 ps/gate has been obtained in the experimental circuit.
All refractory Josephson loop logic circuits for a 1Kbit SFQ memory have been developed. The circuit fabircation technology, using NbN/Nb double layered junction formation and reactive ion etching(RIE)with a 2.5μm minimum feature size and 1.5μm overlay registration, has been utilized. A highly selective and anisotropic RIE process has been performed, in which a CCl2F2+ Ne gas mixture has been used as etching gases. The experimental circuit consists of address decoders and line drivers, which are based on the principle of current steering in superconducting loops. The decoder and driver were successfully operated with the gate current margin of ±18% and ±14%, respectively. The decoder internal delay time was measured to be about 1.5 ns. It is revealed that these circuits have a satisfactory preformance to be used in the 1Kbit SFQ memory.
We have developed a novel process for fabricating all refractory Josephson tunnel junctions whose base and counter electrodes are composed of (Nb-NbN) double-layered films. In this process, tunnel junctions have been isolated using a reactive ion etching from a junction sandwich which had been formed on an entire silicon wafer, and also the reactive ion etching has been used for patterning electrodes and insulation layers in devices. Fabricated junctions have yielded good tunneling characteristics with excellent uniformity and reproducibility. The maximum critical current density was widely changed from 300 A/cm2to 8 kA/cm2. All refractory single flux quantum(SFQ) memory cells in a 32×32 arrangement have been integrated with a 2.5 μm minimum linewidth on a chip using this process, and an SFQ cell in the memory array has been successfully operated. The maximum deviation of critical currents in the memory array was measured to be ±6.5%.
All hard Josephson tunnel junctions, whose base and counter electrodes are composed of double-layered niobium nitride (NbN) and niobium (Nb) films, have been successfully fabricated by isolating a junction sandwich formed on a whole silicon wafer with a reactive ion etching technique. The reactive ion etching technique has been used for patterning both base and counterelectrodes, and self-aligning definition of junction areas has been performed. The fabricated junctions show good quality single-particle tunneling characteristics and excellent uniformity in critical currents.
A novel process suitable for fabricating superconducting circuitry based on the all refractory material NbN is described. In this process, an in-situ trilayer film composed of NbN/MgO/NbN is used to fabricate Josephson tunnel junctions. Reactive ion etching processes are used to delineate devices and pattern insulators and metallizations. Fabricated junctions have yielded good tunneling characteristics with reasonable current density uniformity and reproducibility. Devices with gap voltages close to 5mV have been achieved for high quality junctions. In addition to the trilayer, there are two wiring layers, two resistor depositions, and two insulation layers, constituting a full NbN based fabrication technology. Using this process, we fabricated and successfully tested thin film DC SQUID and time domain reflectometer (TDR) circuits. Preliminary measurements suggest that the critical temperature of these circuits is well within the operating temperature of commercial two-stage closed cycle refrigerators.
Submicron NbN/MgO/NbN Josephson tunnel junctions for Josephson integrated circuits were investigated. The junctions have been fabricated by the cross-line patterning (CLIP) method with an electron-beam (EB) direct-writing technique. The all-refractory fabrication process for logic circuits using the CLIP method is presented. This process is applied to the fabrication of a logic gate of 4JL containing 0.8- mu m-square junctions as an example of digital application. A logic gate has been fabricated by this process, and its characteristics are discussed.>
For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.