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Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Fabrication process of superconducting integrated circuits with submicron Nb/AlO x /Nb junctions using electron-beam direct writing technique

Masahiro Aoyagi, Hiroshi Nakagawa

Published Jul 7, 1997• 2 citations

Abstract

For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.

DOI: 10.1117/12.275805

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For enhancing operating speed of a superconducting integrated circuit (IC), the device size must be reduced into the submicron level. For this purpose, we have introduced electron beam (EB) direct writing technique into the fabrication process of a Nb/AlOx/Nb Josephson IC. A two-layer (PMMA/(alpha) M-CMS) resist method called the portable conformable mask (PCM) method was utilized for having a high aspect ratio. The electron cyclotron resonance (ECR) plasma etching technique was utilized. We have fabricated micron or submicron-size Nb/AlOx/Nb Josephson junctions, where the size of the junction was varied from 2 micrometer to 0.5 micrometer at 0.1 micrometer intervals. These junctions were designed for evaluating the spread of the junction critical current. We achieved minimum-to-maximum Ic spread of plus or minus 13% for 0.81-micrometer-square (plus or minus 16% for 0.67-micrometer-square) 100 junctions spreading in 130- micrometer-square area. The size deviation of 0.05 micrometer was estimated from the spread values. We have successfully demonstrated a small-scale logic IC with 0.9-micrometer-square junctions having a 50 4JL OR-gate chain, where 4JL means four junctions logic family. The circuit was designed for measuring the gate delay. We obtained a preliminary result of the OR- gate logic delay, where the minimum delay was 8.6 ps/gate.

Submicron NbN/MgO/NbN Josephson tunnel junctions for Josephson integrated circuits were investigated. The junctions have been fabricated by the cross-line patterning (CLIP) method with an electron-beam (EB) direct-writing technique. The all-refractory fabrication process for logic circuits using the CLIP method is presented. This process is applied to the fabrication of a logic gate of 4JL containing 0.8- mu m-square junctions as an example of digital application. A logic gate has been fabricated by this process, and its characteristics are discussed.>

Development of 15kA/cm

^2

Fabrication Process for Superconducting Integrated Digital Circuits

A new fabrication process for superconducting integrated digital circuits is reported. We have developed the "SIMIT Nb04" fabrication technique for superconducting integrated circuits with Nb-based Josephson junctions based on the validated "SIMIT Nb03" process and Chemical Mechanical Planarization (CMP) technology. Seven Nb superconducting layers and one Mo resistor layer are included in the "SIMIT Nb04" process with 19 mask levels. The device structure is composed of active layers including junctions at the bottom, two passive transmission line (PTL) layers in the middle and a DC power layer at the top. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistance Rsh of 3

Ω

, followed by the deposition of Nb/Al-AlO

_x

/Nb trilayer Josephson-junction with a target critical current density Jc at 15 kA/cm

^2

. To increase the Al-AlO

_x

barrier layer etching's repeatability, an additional barrier protection layer was applied. To accomplish high-quality planarization, we created a planarization procedure coupled with dummy filling. To assess the process dependability and controllability, a set of process control monitors (PCMs) for monitoring fabrication and design parameters was designed and monitored. The successful manufacturing and testing of a few small-scale circuits, like our standard library cells, further attests to the viability of our fabrication process for superconducting integrated circuits.

Nb/Al–AlO x /Nb tunnel junctions are often used in the studies of macroscopic quantum phenomena and superconducting qubit applications of the Josephson devices. In this work, we describe a convenient and reliable process using electron beam lithography for the fabrication of high-quality, submicron-sized Nb/Al–AlO x /Nb Josephson junctions. The technique follows the well-known selective Nb etching process and produces high-quality junctions with V m = 100 mV at 2.3 K for the typical critical current density of 2.2 kA/cm 2 , which can be adjusted by controlling the oxygen pressure and oxidation time during the formation of the tunnelling barrier. We present the results of the temperature dependence of the sub-gap current and in-plane magnetic-field dependence of the critical current, and compare them with the theoretical predictions.

We present the latest development of an Nb/Al-AlOx/Nb Josephson junction fabrication process for superconducting integrated circuits at SIMIT. Our fabrication process has four niobium superconducting layers and one Ti/Pd resistor layer with 1.0 Ω/square sheet resistor for junction shunting and circuit biasing. Critical current density Jcof the junctions is controlled from 30 A/cm2to 10 kA/cm2by exposing aluminum layer to pure or mixed O2atmosphere. Correlation between measured Jcand exposure conditions has been established. Average quality factor (Rsg/Rn) of the junctions in our process is larger than 20 with subgap leakage factor (Vm) beyond 30 mV. Critical current uniformity is obtained according to the switching current (Is) distribution of a 1000-JJ array. Measured standard deviation sigma of Isis less than 4% over the 100-mm wafer. Plasma resonance in a large Josephson junction is used to measure specific capacitance (Cs) of the junction. Sheet inductances of superconducting niobium strip-lines are extracted by a SQUID diagnose circuit and the measured results show good agreement with our design values.

We have developed a combined photolithography and electron-beam lithography fabrication process for sub-\mum to \mum-size Nb/Al-AlOx/Nb Josephson junctions. In order to define the junction size and protect its top electrode during anodic oxidation, we developed and used the new concept of an aluminum hard mask. Josephson junctions of sizes down to 0.5 \mum2 have been fabricated and thoroughly characterized. We found that they have a very high quality, which is witnessed by the IV curves with quality parameters Vm > 50 mV and Vgap = 2.8 mV at 4.2 K, as well as IcRN products of 1.75-1.93 mV obtained at lower temperatures. In order to test the usability of our fabrication process for superconducting quantum bits, we have also designed, fabricated and experimentally investigated phase qubits made of these junctions. We found a relaxation time of T1 = 26 ns and a dephasing time of T2 = 21 ns.

We have developed a fabrication technology for superconducting integrated circuits with Nb-based Josephson junctions. The standard fabrication process with 10 mask levels includes 3 Nb superconducting layers and a Mo resistor layer. The influence of deposition parameters on film stress, electrical properties, and surface roughness were studied systematically. High quality Nb, Al, Mo, and SiO2films were successfully deposited for the subsequent fabrication of circuits. The circuit fabrication started with the fabrication of Mo resistors with a target sheet resistanceRshof 2 Ω, followed by the deposition of Nb/Al-AlOx/Nb trilayer Josephson-junction. The target critical current densityJcwas set at 6 kA/cm2. Small-scale circuits such as our standard library cells have been successfully fabricated and tested, confirming the capability of our fabrication technology for superconducting integrated circuits.