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IEEE Transactions on Magnetics

Fabrication and performance of all refractory josephson logic circuits for 1 Kbit SFQ memory

Shuichi Tahara, S. Kosaka, Alexandre Shoji, Masahiro Aoyagi, Fujitoshi Shinoki, H. Hayakawa

Published Mar 1, 1985• 5 citations
Publisher

Abstract

All refractory Josephson loop logic circuits for a 1Kbit SFQ memory have been developed. The circuit fabircation technology, using NbN/Nb double layered junction formation and reactive ion etching(RIE)with a 2.5μm minimum feature size and 1.5μm overlay registration, has been utilized. A highly selective and anisotropic RIE process has been performed, in which a CCl2F2+ Ne gas mixture has been used as etching gases. The experimental circuit consists of address decoders and line drivers, which are based on the principle of current steering in superconducting loops. The decoder and driver were successfully operated with the gate current margin of ±18% and ±14%, respectively. The decoder internal delay time was measured to be about 1.5 ns. It is revealed that these circuits have a satisfactory preformance to be used in the 1Kbit SFQ memory.

DOI
10.1109/tmag.1985.1063744

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TECHNOLOGIES FOR THE FABRICATION OF NANOSCALE SUPERCONDUCTING CIRCUITS

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Final Report•Jul 24, 1986•0 citations
All refractory Josephson loop logic circuits for a 1Kbit SFQ memory have been developed. The circuit fabircation technology, using NbN/Nb double layered junction formation and reactive ion etching(RIE)with a 2.5μm minimum feature size and 1.5μm overlay registration, has been utilized. A highly selective and anisotropic RIE process has been performed, in which a CCl2F2+ Ne gas mixture has been used as etching gases. The experimental circuit consists of address decoders and line drivers, which are based on the principle of current steering in superconducting loops. The decoder and driver were successfully operated with the gate current margin of ±18% and ±14%, respectively. The decoder internal delay time was measured to be about 1.5 ns. It is revealed that these circuits have a satisfactory preformance to be used in the 1Kbit SFQ memory.
We have developed a novel process for fabricating all refractory Josephson tunnel junctions whose base and counter electrodes are composed of (Nb-NbN) double-layered films. In this process, tunnel junctions have been isolated using a reactive ion etching from a junction sandwich which had been formed on an entire silicon wafer, and also the reactive ion etching has been used for patterning electrodes and insulation layers in devices. Fabricated junctions have yielded good tunneling characteristics with excellent uniformity and reproducibility. The maximum critical current density was widely changed from 300 A/cm2to 8 kA/cm2. All refractory single flux quantum(SFQ) memory cells in a 32×32 arrangement have been integrated with a 2.5 μm minimum linewidth on a chip using this process, and an SFQ cell in the memory array has been successfully operated. The maximum deviation of critical currents in the memory array was measured to be ±6.5%.
A novel process suitable for fabricating superconducting circuitry based on the all refractory material NbN is described. In this process, an in-situ trilayer film composed of NbN/MgO/NbN is used to fabricate Josephson tunnel junctions. Reactive ion etching processes are used to delineate devices and pattern insulators and metallizations. Fabricated junctions have yielded good tunneling characteristics with reasonable current density uniformity and reproducibility. Devices with gap voltages close to 5mV have been achieved for high quality junctions. In addition to the trilayer, there are two wiring layers, two resistor depositions, and two insulation layers, constituting a full NbN based fabrication technology. Using this process, we fabricated and successfully tested thin film DC SQUID and time domain reflectometer (TDR) circuits. Preliminary measurements suggest that the critical temperature of these circuits is well within the operating temperature of commercial two-stage closed cycle refrigerators.
The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators.>
Researches on the fabrication of ~ 0.1 × 0.1 μ m 2 superconductor–insulator–superconductor (SIS) Josephson junctions are reviewed. Today, a typical dimension is 1–10 μm for Josephson junctions in superconducting integrated circuits. These Josephson junctions are defined by well-established photolithographic technology with reactive ion etching (RIE), and for the superconductor, Nb is almost always used. The merits of Nb include the facts that the superconducting transition temperature Tc of Nb (9.2 K ) is higher than the boiling point of He (4.2 K ), and that Nb has excellent stability against thermal cycling between room temperature and liquid- He temperature. For the fabrication of ~ 0.1 × 0.1 μ m 2 junctions, on the other hand, there is a standard process with electron-beam lithography, shadow evaporation, and lift-off. This process works well for Al (Tc = 1.2 K ), however, it is not ideal for Nb . The scope of this brief review is the nanoscale junction with Nb electrodes. We will look at the efforts of optimizing the standard lift-off process for Nb , electron-beam-lithographic versions of the Nb Josephson-junction technology, focused-ion-beam (FIB) etching as a convenient alternative to electron-beam lithography and RIE, etc. In order to characterize nanoscale tunnel junctions, the single-charge transistor has been often fabricated. Therefore, a summary of its theoretical transport properties is also included.
A novel process suitable for fabrication superconducting circuitry based on the all refactory material NbN is described. In this process, and in-situ trilayer film composed of NbN/MgO/NbN is used to fabricate Josephson tunnel junctions. Reactive ion etching processes are used to delineate devices and pattern insulators and metallizations. Fabricated junctions have yielded good tunneling characteristics with reasonable current density uniformity and reproducibility. Devices with gap voltages close to 3mV have been achieved for high quality junctions (Vm 20 mV). In addition to the trilayer, there are two wiring layers, two resistor depositions, and two insulation layers, constituting a full NbN based fabrication technology. Using this process, we fabricated and successfully tested thin film DC SQUID and time domain reflectometer (TDR) circuits. Preliminary measurements suggest that the critical temperature of these circuits is well within the operating temperature of commercial two-stage closed cycle refrigerators. (Author)