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Electronics and Communications in Japan (Part II Electronics)

Josephson threshold logic circuit and its application

Y. Harada, Yuji Hatano, Kunio Yamashita, Ushio KAWABE

Published Jan 1, 1986• 0 citations
Publisher

Abstract

Abstract This paper proposes a Josephson threshold logic circuit, which is best suited to high‐speed operations. Using the proposed circuit, the adder can be constructed by four Josephson elements. The scale of the circuit can be reduced both in the number of circuits and the number of logic stages, compared with the conventional Josephson logic circuits. The circuit is shown to be useful in the realization of the high‐speed and highly integrated adders and multipliers. Then it is demonstrated that the Josephson threshold logic circuit can be constructed by the magnetically coupled interferometer element, the current‐injection interferometer element and the direct‐coupled element. A typical circuit construction is shown with the adder as an example. To verify the correct operation of the Josephson threshold logic circuit, a 1‐bit adder by magnetically coupled interferometer elements was constructed by Nb‐Pb alloy process, and the operation of the circuit was verified.

DOI
10.1002/ecjb.4420690710

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Electronics and Communications in Japan (Part II Electronics)•Oct 1, 1994•0 citations
Abstract This paper proposes a Josephson threshold logic circuit, which is best suited to high‐speed operations. Using the proposed circuit, the adder can be constructed by four Josephson elements. The scale of the circuit can be reduced both in the number of circuits and the number of logic stages, compared with the conventional Josephson logic circuits. The circuit is shown to be useful in the realization of the high‐speed and highly integrated adders and multipliers. Then it is demonstrated that the Josephson threshold logic circuit can be constructed by the magnetically coupled interferometer element, the current‐injection interferometer element and the direct‐coupled element. A typical circuit construction is shown with the adder as an example. To verify the correct operation of the Josephson threshold logic circuit, a 1‐bit adder by magnetically coupled interferometer elements was constructed by Nb‐Pb alloy process, and the operation of the circuit was verified.
A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.
Detailed investigations have been carried out on a Josephson parallel full adder as an example of a functional circuit using Josephson junctions. This circuit can be constructed with fewer devices as compared with conventional Josephson adders. Two-junction interferometers (d.c.-SQUIDs) are utilized as switching elements of the circuit. Only (2N+1) d.c.-SQUIDs are required for construction of an N bit circuit. Discussions focus on design theory of the full adder circuit. An experimental 4 bit circuit operation is also demonstrated.
A novel Josephson logic gate called the asymmetrical interferometer device (AID) is presented. It is composed of a pair of asymmetrical interferometers whose outputs are injected into a single junction. The interferometers are individually operated as two input OR and the single junction is worked as AND.(A + B) (C + D)operation is accomplished by only one AID gate. They have a serial fan-in capability due to their magnetic coupling scheme. The gate size is reduced by half, compared with the previous current injection logic (CIL) gate. With these AID gates, a high-speed two-bit dual rail adder circuit is configured, which provides the logic circuits performing with both true and complement inputs and without any timing circuits. The AID gate fabricated by standard 5-µm Pb-alloy technology showed a wide margin over ±20 percent that was in good agreement with statically designed characteristics. Experimental adder operation was also successfully performed.
Abstract A carry circuit for Josephson adder has been studied and tested experimentally. For carry calculation, a ripple carry process by asymmetrical interferometric majority gates is employed because it can reduce the gate number‐add time products compared with carry look ahead process by conventional OR‐AND gates. Add time measurement has been performed with these carry circuits connected to dummy sum circuits. Operation speed as fast as 740 ps was obtained for 16‐bit calculation, which shows excellent agreement with computer simulation. By the analysis, it has been clarified that the operation speed is limited by impedance mismatched input lines.
We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.
Abstract DC‐powered Josephson logic gates have the advan tage of being free from operation error due to crosstalk from power current in contrast to ordinary ac‐powered Josephson logic gates. One of these, the HUFFLE (hybrid unlatching flip‐flop logic element) gate using stacked Josephson interferometers (JI) can execute complicated logic functions by itself. Therefore, high‐Speed operation of logic circuits using HUFFLE gates may be expected because the number of logic stages in the circuits is reduced. to investigate the improvement in circuit per formance by using HUFFLE gates with the stacked structure, the authors have fabricated a 6‐bit arithmetic logic unit (ALU) and tested its operation. Two new logic gales, exclusive OR and majority, newly developed using the stacked structure have been developed. the ALU which performs the four functions, AND, OR, exclusive OR, and ADD, is realized with seven logic stages. Ac cordingly, reduction in the number of logic stages and execution time of the ALU by use of the stacked HUF FLE gate family is confirmed.