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IEEE Journal of Solid-State Circuits

A parallel full adder circuit using Josephson junctions

S. Hasuo, Hideo Suzuki, Kouichi Dazai

Published Feb 1, 1981• 3 citations
Publisher

Abstract

Detailed investigations have been carried out on a Josephson parallel full adder as an example of a functional circuit using Josephson junctions. This circuit can be constructed with fewer devices as compared with conventional Josephson adders. Two-junction interferometers (d.c.-SQUIDs) are utilized as switching elements of the circuit. Only (2N+1) d.c.-SQUIDs are required for construction of an N bit circuit. Discussions focus on design theory of the full adder circuit. An experimental 4 bit circuit operation is also demonstrated.

DOI
10.1109/jssc.1981.1051534

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Detailed investigations have been carried out on a Josephson parallel full adder as an example of a functional circuit using Josephson junctions. This circuit can be constructed with fewer devices as compared with conventional Josephson adders. Two-junction interferometers (d.c.-SQUIDs) are utilized as switching elements of the circuit. Only (2N+1) d.c.-SQUIDs are required for construction of an N bit circuit. Discussions focus on design theory of the full adder circuit. An experimental 4 bit circuit operation is also demonstrated.
We describe a one-bit full adder circuit constructed from direct-coupled Josephson logic elements. The basic gate, which can perform various logic functions, consists of two Josephson junctions and two resistors connected in a loop. Switching the junctions into the finite-voltage state diverts the bias current into a parallel output line, which is directly coupled through the junctions of successive logic elements. The adder is constructed with a 100 μm basic linewidth and 25 μm square tin tunnel junctions. It operates under all input data conditions with an add time of about 1 nS and a power dissipation of 1 μW per gate.
A Josephson two-bit full adder circuit with wide margin functional gates has been studied. The adder circuit is comprised of functional exclusive-OR (EXOR) gates for sum operation and majority gates for ripple carry operation. A wide margin EXOR gate was constructed with serial connection of two double-input asymmetrical interferometers (AILs), in which two input lines were coupled to the interferometers with such an arrangement that the input-induced magnetic fluxes electromagnetically cancel each other. For majority gates, gate-to-input coupling should be made uniform for all three inputs. For this purpose, three input lines were laid in parallel on the loop of triple-input planar interferometer, so that one of two outer lines ran along the loop outside the edge but returned along the inside and the other vice versa. By using these functional gates a full adder circuit can be constructed with only three gates/bits. Experimentally, the two-bit parallel adder circuit was fabricated by standard Pb-alloy technology with 5μm line width. Two-bit parallel full adder operation was successfully performed. Additionally, operating margin over ±10% for the bias was obtained for each gate.
We present the design and the fabrication of an adder circuit in the extended phase-mode logic family. The phase-mode logic is a single flux quantum (SFQ) logic which utilizes an SFQ as an information bit carrier. The single-bit adder circuit is made up of an INHIBIT gate which is the basic device of the phase-mode logic. The circuit has been designed and fabricated using Nb/AlO/sub x//Nb Josephson junctions with Josephson critical current density of 1.0 kA/cm/sup 2/. In order to confirm the circuit operation, the fabricated adder circuit has been tested at low speed. For investigating the possibility of a high-frequency operation, dc voltages generated by fluxon pulse trains have been measured. From the Josephson voltage-frequency relation, the result shows that the circuit has potential to complete the carry operation within 20 psec.
A novel complementary ternary logic circuit using Josephson junctions as switching gates is described. The principle of the circuit is based on the tristate of a Josephson junction, that is the state of switching in either positive direction or negative direction, in addition to the state of no switching. The JCTL is constructed of two SQUIDs (superconducting quantum interference devices), one of which is switched in the positive directions and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, and NOT in ternary form and can function as a full adder if the voltage-current characteristics of the two SQUIDs are adjusted appropriately. The advantage of the JCTL is its higher speed of operation with higher density than the conventional Josephson binary logic circuit. The principle of operation is described in detail, and simulation results are presented.>
Abstract This paper proposes a Josephson threshold logic circuit, which is best suited to high‐speed operations. Using the proposed circuit, the adder can be constructed by four Josephson elements. The scale of the circuit can be reduced both in the number of circuits and the number of logic stages, compared with the conventional Josephson logic circuits. The circuit is shown to be useful in the realization of the high‐speed and highly integrated adders and multipliers. Then it is demonstrated that the Josephson threshold logic circuit can be constructed by the magnetically coupled interferometer element, the current‐injection interferometer element and the direct‐coupled element. A typical circuit construction is shown with the adder as an example. To verify the correct operation of the Josephson threshold logic circuit, a 1‐bit adder by magnetically coupled interferometer elements was constructed by Nb‐Pb alloy process, and the operation of the circuit was verified.