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IEEE Transactions on Applied Superconductivity

A novel Josephson ternary multiplier

Michitada Morisue, Jun Endo, T. Morooka, Yuki Kogure, Akinori Kanasugi

Published Jun 1, 1997• 2 citations
Publisher

Abstract

A novel Josephson ternary logic circuit to perform multiplication is proposed. The fundamental circuit of the multiplier is based on Josephson complementary ternary logic circuit (JCTL). In this paper the principle of the ternary multiplier is described. We have fabricated the multiplier using SQUIDs which were made of Nb/AlOx/Al/Nb junctions, and measurements of the logic operation of the circuit were carried out. The results showed satisfactory operation of the multiplier, which agreed well with the results of simulation. The advantages of the proposed ternary multiplier are capability of ultra-high speed computation, low power consumption and very simple construction with less number of elements to perform a ternary multiplication.

DOI
10.1109/77.621943

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A novel Josephson ternary logic circuit to perform multiplication is proposed. The fundamental circuit of the multiplier is based on Josephson complementary ternary logic circuit (JCTL). In this paper the principle of the ternary multiplier is described. We have fabricated the multiplier using SQUIDs which were made of Nb/AlOx/Al/Nb junctions, and measurements of the logic operation of the circuit were carried out. The results showed satisfactory operation of the multiplier, which agreed well with the results of simulation. The advantages of the proposed ternary multiplier are capability of ultra-high speed computation, low power consumption and very simple construction with less number of elements to perform a ternary multiplication.
A novel complementary ternary logic circuit using Josephson junctions as switching gates is described. The principle of the circuit is based on the tristate of a Josephson junction, that is the state of switching in either positive direction or negative direction, in addition to the state of no switching. The JCTL is constructed of two SQUIDs (superconducting quantum interference devices), one of which is switched in the positive directions and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, and NOT in ternary form and can function as a full adder if the voltage-current characteristics of the two SQUIDs are adjusted appropriately. The advantage of the JCTL is its higher speed of operation with higher density than the conventional Josephson binary logic circuit. The principle of operation is described in detail, and simulation results are presented.>
A novel Josephson complementary ternary logic (JCTL) circuit is described. This fundamental circuit is based on the combination of two SQUIDs (superconducting quantum interference devices), one of which is switched in the positive direction and the other in the negative direction. The JCTL can perform the fundamental operations of AND, OR, NOT, and Double NOT in ternary form. The principle of the operation and design criteria are described in detail. Simulation results show that reliable operation of these circuits can be achieved with a high performance.>
This paper presents a novel Josephson converter to perform signal conversion from a binary system to a ternary system. Most converters perform conversion in successive steps from the least significant bit to the most significant bit. Therefore, the circuits become complicated and operation speed becomes low. In order to overcome these shortcomings, a novel converter based on Josephson technology is proposed. The principle of the converter is described in detail and simulation results for an 8-bit converter are illustrated. The advantages of this converter are simple construction with a small number of elements and high speed operation.>
A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.
Reversible ternary circuit design is now being taken into consideration for its application within the quantum computer and other technologies associated with the nanotechnology domain, in addition to the advantages of the ternary logic application as opposed to binary logic. Multiplier circuit is one of the most important computing circuit in the ALU. Therefore, the circuit optimization for the multiplication will lead to efficient processor. In this paper, the reversible circuit for multiplication of two unsigned two-digit ternary numbers has been proposed. To construct reversible ternary multiplier, a new component termed TPPG with the quantum cost of 13 for partial product generation was proposed. In addition, we have introduced four new blocks of reversible ternary adder with the quantum cost of 11, 10, 7, 5 and one constant input, which can be used in the proposed multiplier circuit. We attempted to optimize the design of the circuits in terms of quantum cost, a number of primitive gates, constant inputs, and garbage outputs as far as possible. To realize all proposed circuits, one-qutrit shift gates and two-qutrit Muthukrishnan-Stroud gates were used.
Abstract This paper proposes a Josephson threshold logic circuit, which is best suited to high‐speed operations. Using the proposed circuit, the adder can be constructed by four Josephson elements. The scale of the circuit can be reduced both in the number of circuits and the number of logic stages, compared with the conventional Josephson logic circuits. The circuit is shown to be useful in the realization of the high‐speed and highly integrated adders and multipliers. Then it is demonstrated that the Josephson threshold logic circuit can be constructed by the magnetically coupled interferometer element, the current‐injection interferometer element and the direct‐coupled element. A typical circuit construction is shown with the adder as an example. To verify the correct operation of the Josephson threshold logic circuit, a 1‐bit adder by magnetically coupled interferometer elements was constructed by Nb‐Pb alloy process, and the operation of the circuit was verified.