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IEEE Transactions on Applied Superconductivity

Design and demonstration of SFQ pipelined multiplier

A. Akahori, Masamitsu Tanaka, A. Sekiya, Akira Fujimaki, Hisao Hayakawa

Published Jun 1, 2003• 10 citations
Publisher

Abstract

We have designed an SFQ pipeline multiplier using a cell-based design method. The cell-based design method enables us to expand the circuit-scale easily and is essential for the design of large-scale circuits. In the construction of the multiplier, a serial-parallel type was adopted. This type performs the partial products and the summation of the products in a bit-serial form. The multiplier designed here is a 3-bit serial-parallel structure with a seven-stage pipeline and is composed of destructive read-out (DRO) gates, nondestructive read-out (NDRO) gates and carry save serial adders (CSSA's). This circuit was fabricated by the NEC standard process. The number of Josephson Junctions is 1150. We have successfully tested the full operation with a bias margin of /spl plusmn/5.5%.

DOI
10.1109/tasc.2003.813946

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IEEE Transactions on Applied Superconductivity•Jan 7, 2011•10 citations
We have designed an SFQ pipeline multiplier using a cell-based design method. The cell-based design method enables us to expand the circuit-scale easily and is essential for the design of large-scale circuits. In the construction of the multiplier, a serial-parallel type was adopted. This type performs the partial products and the summation of the products in a bit-serial form. The multiplier designed here is a 3-bit serial-parallel structure with a seven-stage pipeline and is composed of destructive read-out (DRO) gates, nondestructive read-out (NDRO) gates and carry save serial adders (CSSA's). This circuit was fabricated by the NEC standard process. The number of Josephson Junctions is 1150. We have successfully tested the full operation with a bias margin of /spl plusmn/5.5%.
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.
The authors have designed, fabricated, and tested a Josephson bit serial multiplier based on voltage latching logic. The bit serial implementation takes advantage of high-speed characteristics of Josephson circuits to achieve higher circuit functionality per gate by reducing gate complexity. To facilitate the multiplier design, logic simulation was performed using transistor-transistor-logic (TTL) equivalent gate models of voltage latching modified-variable-threshold-logic (MVTL) gates. A 4-b serial-parallel multiplier based on MVTL gates has been designed and fabricated in niobium. The basic timed-XOR and full adder circuits used in the multiplier were successfully tested. Preliminary testing of the multiplier indicated inadequate operating margin for a full functional test.>
We will discuss the microarchitecture, design, and testing of the first 8 × 8-bit (by modulo 256) parallel carry-save RSFQ multiplier implemented using the ISTEC 10- kA/cm21.0-μm fabrication technology. Partial products are asynchronously generated and sent to the reduction stage at the internal “hardwired” rate of 80 GHz. The 8 × 8-bit RSFQ multiplier uses a two-level parallel carry-save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data-driven wave-pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly regular layout with both local and global connections between modules. The multiplier core (without SFQ-to-DC and DC-to-SFQ converters) has 5948 Josephson junctions occupying the area of 3.5 mm2. The multiplier is designed with the target operation frequency of 20 GHz and has the latency of 447 ps at the bias voltage of 2.5 mV. Despite some challenges due to fabrication process parameter variations and flux trapping, the multiplier chip was fabricated and successfully tested for the vast majority of test vectors by the Stony Brook designers with the assistance of colleagues from Yokohama National University in February 2012. While multiplier test operations were generated at low frequency, each of these operations was executed at the “hardwired” rate of 80 GHz. The fabricated chip operated with the measured DC bias margins of ±5%.
We have designed a Rapid Single-Flux-Quantum (RSFQ) bit-serial real-time pipeline multiplier for digital signal processing (DSP) applications. A single-bit module of this multiplier consists of 96 Josephson junctions and uses a B-flip-flop-based carry-save adder (CSA). For HYPRES' standard 1-kA/cm/sup 2/ Nb process with 3.5 /spl mu/m-diameter Josephson junctions the module occupies all area of 350/spl times/600 /spl mu/m/sup 2/. Simulations show that the circuit should dissipate 28 /spl mu/W of power at 2.6 mV dc supply voltage and operate at frequencies of up to 25 GHz. We have successfully tested all cells of the module and verified correct operation of a simplified version of the module at low frequencies. According to numerical simulations, the speed of the multiplier is limited by the CSA. In order to overcome this bottleneck we have developed a concept of a fast carry-save pipeline adder based on XOR gates which uses an RSFQ-specific algorithm for carry bit calculation.>
We have designed a high-speed SFQ bit-serial carry-save adder based on the binary decision diagram (BDD). A simple bit-serial carry-save adder based on the BDD we first designed has a carry-feedback loop. Its input data frequency is limited by the propagation delay in the feedback loop. In our second adder design, we have replaced one BDD gate with a nondestructive binary switch, by which we can eliminate the carry-feedback loop. We have designed the high-speed BDD SFQ bit-serial adder using the NEC 2.5 kA cm −2 Nb standard process and the CONNECT cell library. The circuit simulation indicates that the maximum operating frequency is 38 GHz and the dc bias margin at 10 GHz is ±23%. We have confirmed its correct operation in the on-chip high-speed test. The maximum operating frequency was found to be 23.8 GHz.
We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.