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IEEE Transactions on Applied Superconductivity

4-bit SFQ Multiplier Based on Booth Encoder

Ryosuke Nakamoto, 栄 桜庭, Takeshi Onomi, Shigeo Sato, Koji Nakajima

Published Jan 7, 2011• 10 citations
Publisher

Abstract

We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.

DOI
10.1109/tasc.2010.2095814

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We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.
We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2/spl times/2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45% fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of /spl plusmn/9.5%.
To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 4 x 4 switch having block-to-block passive interconnections and a 2 x 2 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFO circuits having passive interconnections.
We have designed an SFQ pipeline multiplier using a cell-based design method. The cell-based design method enables us to expand the circuit-scale easily and is essential for the design of large-scale circuits. In the construction of the multiplier, a serial-parallel type was adopted. This type performs the partial products and the summation of the products in a bit-serial form. The multiplier designed here is a 3-bit serial-parallel structure with a seven-stage pipeline and is composed of destructive read-out (DRO) gates, nondestructive read-out (NDRO) gates and carry save serial adders (CSSA's). This circuit was fabricated by the NEC standard process. The number of Josephson Junctions is 1150. We have successfully tested the full operation with a bias margin of /spl plusmn/5.5%.
We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.
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A high-throughput 4$\boldsymbol{\times }4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm4−bitmultiplierwasdemonstratedusinganextremelycarefultimingdesignforlow−voltagerapidsingle−flux−quantum(LV−RSFQ)logic.Thedesignconsidersthelengthsofallwires,biasdependencyofthedelays,andloaddependencyofthesignalsplitters.ThekeyistointentionallyusebothJosephsontransmissionlinesandpassivetransmissionlinesforgate−to−gatewiring,evenovershortdistances,toformthesamestructurewiringastheclocklines.Thestructureofthemultiplierisbasedonabit−parallel,gate−levelpipelinetoexploitthroughput.ThetestchipwasfabricatedusingtheAIST10−kA/cm\boldsymbol{^2},Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134, Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134,Nb/AlOx/Nb,9−Nb−layerAdvancedProcess2.Themeasuredmaximumoperatingfrequency,throughput,andpowerconsumptionwithoutcoolingcostinthehigh−speedon−chiptestwere52GHz,52G−operationspersecond(GOPS),and134\boldsymbol{\mu }W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40W, respectively. Although the switching speed of the Josephson junctions was reduced by 40W,respectively.AlthoughtheswitchingspeedoftheJosephsonjunctionswasreducedby40\boldsymbol{\%}$owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.