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IEEE Transactions on Applied Superconductivity

Frequency Multiply Circuit for Superconducting A/D Converter

Akira Yoshida, S. Hirano, Hideo Suzuki, S. Hasuo, K. Tanabe, Takuma Ito, T. Himi, Hiroshi Takai

Published Jun 1, 2005• 4 citations
Publisher

Abstract

A new frequency multiply circuit generating a 20 GHz sampling clock from an external 5 GHz signal for a lowpass sigma-delta modulator was proposed and designed. The multiply circuit was composed of a ladder circuit, a modified Josephson transmission line (JTL) and T-flip flop (T-FF). We confirmed by numerical simulation that the period jitter of SFQ pulse trains generated by the ladder circuit could be reduced to a value small enough to realize 14-bit resolution for 10 MHz bandwidth by utilizing the repulsion effect between SFQ pulses in the modified JTL. The multiply circuit was fabricated by a 2.5 kA/cm/sup 2/ Nb process, and its correct operation was confirmed.

DOI
10.1109/tasc.2005.849867

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A new frequency multiply circuit generating a 20 GHz sampling clock from an external 5 GHz signal for a lowpass sigma-delta modulator was proposed and designed. The multiply circuit was composed of a ladder circuit, a modified Josephson transmission line (JTL) and T-flip flop (T-FF). We confirmed by numerical simulation that the period jitter of SFQ pulse trains generated by the ladder circuit could be reduced to a value small enough to realize 14-bit resolution for 10 MHz bandwidth by utilizing the repulsion effect between SFQ pulses in the modified JTL. The multiply circuit was fabricated by a 2.5 kA/cm/sup 2/ Nb process, and its correct operation was confirmed.
In order to establish double-loop feedback design, we have fabricated a prototype superconducting double-loop lowpass sigma-delta modulator. For digital feedback gain, multiple flux quanta are produced by a ladder circuit and carried through Josephson Transmission Lines (JTLs) to the feedback driver. The feedback driver consists of a single Josephson junction or two serially-connected junctions. Direct injection of the pulse current from the JTLs through a low-value resistor drives the feedback driver. The sigma-delta modulator was operated at the sampling frequency of 1.1 GHz and the measured power spectrum showed the noise shaping roughly of 12 dB/octave, which is characteristic of the second-order sigma-delta modulator.
We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlO x /Nb junction technology with J c = 2.5 kA cm -2 . We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing I c . As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.
We have proposed a multi-bit sigma-delta analog-to-digital converter (ADC) in which a modulator is composed of a single quantizer and multiple samplers based on the single-flux-quantum (SFQ) circuits. The quantizer converts analog signals to pulse-density-modulated signals, and the samplers sample the modulated SFQ pulses in every sampling clock. Use of multiple samplers based on delayed-flip-flops (DFFs) increases sampling frequencies virtually, resulting in a multi-bit sigma-delta modulator. We also designed a decimation filter by using the well-established Verilog tools for the SFQ circuits and the Matlab simulator. We prepared an ADC including 4 samplers and a second-order decimation filter with the decimation rate of 1:256 based on the Nb junction technology. We confirmed correct operation of this ADC at 56 GHz clock signals generated by an internal ring oscillator. We experimentally obtained the signal-to-noise ratio of 25 dB and spurious-free dynamic range of 37 dB at the bandwidth of 10 MHz from the upper 7 bits of the outputs of the decimation filter.
We have designed a 2-bit Booth encoder with Josephson Transmission Lines (JTLs) and Passive Transmission Lines (PTLs) by using cell-based techniques and tools. The Booth encoding method is one of the algorithms to obtain partial products. With this method, the number of partial products decreases down to the half compared to the AND array method. We have fabricated a test chip for a multiplier with a 2-bit Booth encoder with JTLs and PTLs. It has a processing frequency of 20 GHz with the bias margin ±25%. The frequency of this circuit increases up to 45 GHz with the bias voltage by 25% increased from the design voltage. The circuit area of the multiplier designed with the Booth encoder method is compared to that designed with the AND array method.
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.
We designed a front-end circuit for an analog-to-digital (A/D) converter based on single flux quantum circuitry and tested its functionality at a frequency of up to 43 GHz. The front-end circuit consisted of a pulse generator, a sigma-delta modulator, a 1-to-8 demultiplexer (DEMUX), and superconducting quantum interference device (SQUID) amplifiers. There were 2518 Josephson junctions in the front-end circuit. To operate the circuit at high speed, we designed robust timing against variations in circuit parameters. By using circuit simulations based on the Monte Carlo method, we estimated spread in time lag between clock and data pulses. From this estimate, the timing was optimized to operate the circuit at 40 GHz. The demonstration of the front-end circuit was carried out using the on-chip testing method. Output data were acquired from the modulator through DEMUX. We confirmed proper sigma-delta modulation by analyzing the dependence of the density "1" in the output data on input current level. The proper operation was confirmed in a range of 37-43 GHz. Furthermore, the amplification by the SQUID amplifier was also confirmed at low speed. These results indicate the complete operation of the front-end circuit for superconductive A/D converter.