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IEEE Transactions on Applied Superconductivity

Improvement of Operating Margin of SFQ Circuits by Controlling Dependence of Signal Propagation Time on Bias Voltage

Mikio Otsubo, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Dec 13, 2012• 5 citations
Publisher

Abstract

Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.

DOI
10.1109/tasc.2012.2234176

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Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. However, the operating margin of these circuits decreases with an increase in the operating frequency because a timing error occurs in the low bias region. In this study, a novel design method that enables a wide operating margin at a high operating frequency has been investigated. The proposed circuits incorporate an additional bias feeding line in addition to the conventional bias feeding lines of the conventional Josephson transmission lines (JTLs) and can control the dependence of signal propagation time on the bias voltage. We have shown experimentally that in our proposed JTLs, the signal propagation time becomes more sensitive to the bias voltage. Timing errors can be avoided by inserting proposed JTL cells in the critical data path of the SFQ digital circuits. Circuit simulation results indicate that the operating margin of a bit-serial SFQ full adder, designed assuming the 2.5 kA/cm2Nb process, can be improved by 15% compared with the conventional design at a frequency of 20 GHz by employing our novel design method.
Superconductive single flux quantum (SFQ) digital circuits can operate at a clock frequency of several tens of gigahertz. The operating margin of an SFQ logic circuit generally decreases with an increase in the operating frequency because of the timing error in the low-bias region caused by the difference in bias dependence of the signal-propagation delay between the data and clock lines. We proposed an improvement in the operating margin by controlling the dependence of the signal-propagation time on the bias voltage. In the present study, we investigated a new optimization method for an SFQ logic gate. We developed a new circuit parameter optimizer, which takes into account not only the bias margin but also the dependence of the signal-propagation delay on the bias voltage. We defined an appropriate evaluation function for the optimization. From the result of the optimization using the defined evaluation function, we designed and demonstrated an SFQ AND gate optimized using the new optimizer.
Energy efficiency has become the primary parameter for the design of next-generation single flux quantum (SFQ) circuits. This, however, needs to be balanced with optimization for clock speed and bias margins. Here, we experimentally study the tradeoff between circuit activity, energy efficiency, and bias margins for zero static power dissipation ERSFQ circuits. For ERSFQ, dc power is provided by a Josephson transmission line (JTL) called a “feeding” JTL (FJTL), which acts as a voltage source. As a test case, shift registers and multiplexers were laid out and fabricated in both HYPRES's and MIT-LL's 10-kA/cm2fabrication processes and tested at low (~kHz) and high (~GHz) clock frequencies. The functional bias margins for these circuits increase significantly from +/-4% to over +/-19% when the Josephson junction count in the FJTL was increased to ~30% of total dc bias current of the circuit. Based on our findings, we discuss how to optimize ERSFQ circuits for both energy efficiency and dc bias margins.
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100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2{\rm kA/cm}^{2}kA/cm2 Niobium Process
This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.
Abstract As a member of the superconducting integrated circuit family, energy-efficient rapid single flux quantum (ERSFQ) circuit combines low-power consumption with high frequency, showing promise for application in high-energy efficient neuromorphic computing and traditional high-performance computing. Previous studies have demonstrated that there are typically two energy dissipation states in working ERSFQ circuits: energy-efficient SFQ state (E-state) and resistive-biased SFQ state (R-state). These states occur at different biasing current ranges, and the sum of the bias margin of these two states is close to the margin of rapid single flux quantum (RSFQ) circuits of the same design. For ultra-low-power applications, the bias current margin of the R-state must be excluded, leading to a substantially narrower bias margin in ERSFQ circuits than in their RSFQ counterparts. In our previous research, we proposed the feeding pulse method to increase the bias current margin by extending the lower boundary of the E-state through the injection of feeding pulses into the feeding Josephson transmission line (FJTL). In this study, we further investigated the current distribution mechanism in ERSFQ circuits and, based on this, proposed a method of optimizing design of the FJTL to redirect excess current to the FJTL, so as to expand the upper boundary of the E-state’s bias current margin. We tested an ERSFQ 8-bit shift register of the ERSFQ by applying methods proposed in this work together with the feeding pulses method proposed before. The results demonstrated that the bias current margin of the E-state expanded from (94%, 98%) to (56%, 116%), corresponding to a 14-times increase, with both the lower and upper boundary successfully extended. Our research addresses the issue of limited current bias margin in ERSFQ circuits during actual operation, providing a more robust ERSFQ technology for future applications in neural networks and high-performance computing.
In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.