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arXiv:2312.13350

Improving fidelity of multi-qubit gates using hardware-level pulse parallelization

Sagar Silva Pratapsi, Diogo Cruz

Published Dec 20, 2023• 0 citations
arXivHTMLPDF

Abstract

Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on $R_{ZX}$ gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking, our most modest fidelity gain was from 98.16(7)% to 99.15(3)% for the application of two $R_{ZX}(π/2)$ gates with one shared qubit. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.

DOI
10.48550/arxiv.2312.13350

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Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on RZXR_{ZX}RZX​ gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking, our most modest fidelity gain was from 98.16(7)% to 99.15(3)% for the application of two RZX(π/2)R_{ZX}(π/2)RZX​(π/2) gates with one shared qubit. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.
Abstract Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on RZXR_{ZX}RZX​ R ZX gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking and Process Tomography, we reduce gate errors by half. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.
We show a pulse-efficient circuit transpilation framework for noisy quantum hardware. This is achieved by scaling cross-resonance pulses and exposing each pulse as a gate to remove redundant single-qubit operations with the transpiler. Crucially, no additional calibration is needed to yield better results than a CNOT-based transpilation. This pulse-efficient circuit transpilation therefore enables a better usage of the finite coherence time without requiring knowledge of pulse-level details from the user. As demonstration, we realize a continuous family of cross-resonance-based gates for SU(4) by leveraging Cartan's decomposition. We measure the benefits of a pulse-efficient circuit transpilation with process tomography and observe up to a 50% error reduction in the fidelity of ${R}_{ZZ}(\ensuremath{\theta})$ and arbitrary SU(4) gates on IBM Quantum devices. We apply this framework for quantum applications by running circuits of the quantum approximate optimization algorithm applied to MAXCUT. For an 11-qubit nonhardware native graph, our methodology reduces the overall schedule duration by up to 52% and errors by up to 38%.
We propose and validate on real quantum computing hardware a new method for extended two-qubit gate set design, replacing iterative, fine calibration with fast characterization of a small number of gate parameters which are then tracked and corrected in circuit compilation. Coherent contributions to the pulse unitary that would traditionally be considered sources of error are treated as part of the gate definition, and compensated in software via single-qubit rotations. This approach enables rapid device-wide generation of high-fidelity two-qubit entangling gates, which are combined with standard calibrated gates to produce an expanded gate set. We show how these gates are directly usable as part of a quantum compiler, synthesizing generic two-qubit circuit blocks into minimal-duration sequences of the characterized gates interleaved with compensating single-qubit rotations. Benchmarking against circuits compiled using the default CXCXCX gate alone on 127-qubit IBM hardware shows up to 7X improvement in success probability for Quantum Fourier Transform circuits up to 26 qubits, and up to 9X lower mean-square error in Trotter simulations of the one-dimensional transverse-field Ising model. Our hardware-agnostic characterization and compilation methodology makes it practical to scale up expressive gate sets on quantum computing architectures while minimizing the need for onerous fine-tuning of low-level control waveforms.
Abstract Benchmarking large-scale quantum gates, typically involving multiple native two-qubit and single-qubit gates, is crucial in quantum computing. Global fidelity, encompassing information about inter-gate correlations, offers a comprehensive metric for evaluating and optimizing gate performance, unlike the fidelities of individual local native gates. In this work, utilizing the character-average benchmarking protocol implementable in a shallow circuit, we successfully benchmark gate fidelities up to 52 qubits. Notably, we achieved a fidelity of 63.09% ± 0.23% for a 44-qubit parallel CZ gate. Utilizing the global fidelity of the parallel CZ gate, we explore the correlations among local CZ gates by introducing an inter-gate correlation metric, enabling one to simultaneously quantify crosstalk error when benchmarking gate fidelity. Finally, we apply our methods in gate optimization. By leveraging global fidelity for optimization, we enhance the fidelity of a 6-qubit parallel CZ gate from 87.65% to 92.04% and decrease the gate correlation from 3.53% to 3.22%, compared to local gate fidelity-based optimization. The experimental results align well with our established composite noise model, incorporating depolarizing and Z Z-coupling noises, and provide valuable insight into further study and mitigation of correlated noise.
In the near-term noisy intermediate-scale quantum (NISQ) era, high noise will significantly reduce the fidelity of quantum computing. What's worse, recent works reveal that the noise on quantum devices is not stable, that is, the noise is dynamically changing over time. This leads to an imminent challenging problem: At run-time, is there a way to efficiently achieve a consistent high-fidelity quantum system on unstable devices? To study this problem, we take quantum learning (a.k.a., variational quantum algorithm) as a vehicle, which has a wide range of applications, such as combinatorial optimization and machine learning. A straightforward approach is to optimize a variational quantum circuit (VQC) with a parameter-shift approach on the target quantum device before using it; however, the optimization has an extremely high time cost, which is not practical at run-time. To address the pressing issue, in this paper, we proposed a novel quantum pulse-based noise adaptation framework, namely QuPAD. In the proposed framework, first, we identify that the CNOT gate is the fidelity bottleneck of the conventional VQC, and we employ a more robust parameterized multi-qubit gate (i.e., Rzx gate) to replace CNOT gate. Second, by benchmarking Rzx gate with different parameters, we build a fitting function for each coupling qubit pair, such that the deviation between the theoretic output of Rzx gate and its on-device output under a given pulse amplitude and duration can be efficiently predicted. On top of this, an evolutionary algorithm is devised to identify the pulse amplitude and duration of each Rzx gate (i.e., calibration) and find the quantum circuits with high fidelity. Experiments show that the runtime on quantum devices of QuPAD with 8–10 qubits is less than 15 minutes, which is up to 270 x faster than the parameter-shift approach. In addition, compared to the vanilla VQC as a baseline, QuPAD can achieve 59.33% accuracy gain on a classification task, and average 66.34% closer to ground state energy for molecular simulation.
ABSTRACT: Recent research has tackled the problem of mitigating noise present in quantum computers in the Noisy Intermediate-Scale Quantum (NISQ) era to enable precise computations and to benefit from the intrinsic properties of quantum mechanics. For this matter, an important task is the characterization of qubits available in quantum devices so as to provide insights on how to reduce noise on the final output of a quantum circuit. Characterization comprises analysis of noise sources and this information can be used to reduce noise with methods such as Cycle Benchmarking, Quantum Error Mitigation, Quantum Error Correction and others. Here, we study optimization of pulses through Quantum Optimal Control (QOC) to obtain higher gate fidelity. We will explore an algorithm that performs calibration on specific quantum gates by implementing optimized pulse schedules to subsequently use the algorithm for analysis of noise sources. Using calibrated gates as input, several benchmarking protocols, including pulse noise extrapolation, leakage analysis from quantum optimal control, and machine learning based classification of qubit readout, will be tested to extract precise information on how noise influences the analyzed qubits. We will explain and discuss different techniques for obtaining properties of qubits and quantum computers. We will implement state discrimination with a Machine Learning (ML) focus to analyze readout errors caused by factors such as cross-talk and leakage into higher quantum states. We will perform noise fitting of optimized pulses and evaluate the effectiveness of important quantum algorithms at the pulse level.