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arXiv:2505.22390 · npj Quantum Information

Calibrating quantum gates up to 52 qubits in a superconducting processor

Daojin Fan, Guoding Liu, Shaowei Li, Ming Gong, Dachao Wu, Yiming Zhang, Chen Zha, Fusheng Chen, Sirui Cao, Yangsen Ye, Qingling Zhu, Chong Ying, Shaojun Guo, Haoran Qian, Yulin Wu, Huiqiu Deng, Gang Wu, Cheng-Zhi Peng, Xiongfeng Ma, Xiaobo Zhu, Jian-Wei Pan

Published Feb 26, 2025• 6 citations
arXivHTMLPDF

Abstract

Abstract Benchmarking large-scale quantum gates, typically involving multiple native two-qubit and single-qubit gates, is crucial in quantum computing. Global fidelity, encompassing information about inter-gate correlations, offers a comprehensive metric for evaluating and optimizing gate performance, unlike the fidelities of individual local native gates. In this work, utilizing the character-average benchmarking protocol implementable in a shallow circuit, we successfully benchmark gate fidelities up to 52 qubits. Notably, we achieved a fidelity of 63.09% ± 0.23% for a 44-qubit parallel CZ gate. Utilizing the global fidelity of the parallel CZ gate, we explore the correlations among local CZ gates by introducing an inter-gate correlation metric, enabling one to simultaneously quantify crosstalk error when benchmarking gate fidelity. Finally, we apply our methods in gate optimization. By leveraging global fidelity for optimization, we enhance the fidelity of a 6-qubit parallel CZ gate from 87.65% to 92.04% and decrease the gate correlation from 3.53% to 3.22%, compared to local gate fidelity-based optimization. The experimental results align well with our established composite noise model, incorporating depolarizing and Z Z-coupling noises, and provide valuable insight into further study and mitigation of correlated noise.

DOI
10.1038/s41534-025-00983-5

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Abstract Benchmarking large-scale quantum gates, typically involving multiple native two-qubit and single-qubit gates, is crucial in quantum computing. Global fidelity, encompassing information about inter-gate correlations, offers a comprehensive metric for evaluating and optimizing gate performance, unlike the fidelities of individual local native gates. In this work, utilizing the character-average benchmarking protocol implementable in a shallow circuit, we successfully benchmark gate fidelities up to 52 qubits. Notably, we achieved a fidelity of 63.09% ± 0.23% for a 44-qubit parallel CZ gate. Utilizing the global fidelity of the parallel CZ gate, we explore the correlations among local CZ gates by introducing an inter-gate correlation metric, enabling one to simultaneously quantify crosstalk error when benchmarking gate fidelity. Finally, we apply our methods in gate optimization. By leveraging global fidelity for optimization, we enhance the fidelity of a 6-qubit parallel CZ gate from 87.65% to 92.04% and decrease the gate correlation from 3.53% to 3.22%, compared to local gate fidelity-based optimization. The experimental results align well with our established composite noise model, incorporating depolarizing and Z Z-coupling noises, and provide valuable insight into further study and mitigation of correlated noise.
High-Precision Calibration Workflow Achieves Above 99.9%99.9\%99.9% CZ Gate Fidelity on a Scalable Superconducting Processor
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With the continued scaling of quantum processors, holistic benchmarks are essential for extensively evaluating device performance. Layer fidelity is a benchmark well-suited to assessing processor performance at scale. Key advantages of this benchmark include its natural alignment with randomized benchmarking (RB) procedures, crosstalk awareness, fast measurements over large numbers of qubits, high signal-to-noise ratio, and fine-grained information [1]. In this work, we extend the analysis of the original layer fidelity manuscript to optimize parameters of the benchmark and extract deeper insights of its application. We present a robust protocol for identifying optimal qubit chains of arbitrary lengthNNN, demonstrating that our method yields error per layered gate (EPLG) values40%−70%40 \% - 70 \%40%−70%lower than randomly selected chains forN=100N=100N=100qubits. We further establish layer fidelity as an effective performance monitoring tool, capturing both edge-localized and device-wide degradation by tracking optimal chains of length 50 and 100, and fixed chains of length 100. Additionally, we refine error analysis by proposing parameter bounds on the number of randomizations and Clifford lengths used in direct RB fits, minimizing fit uncertainties. Finally, we use layer fidelity to analyze the impact of varying gate durations on layered two-qubit (2Q) errors, showing that prolonged gate times leading to idling times significantly increase these quantities. These findings extend the applicability of the layer fidelity benchmark and provide practical guidelines for optimizing quantum processor evaluations.
Single-qubit gates on superconducting quantum processors are typically implemented using microwave pulses applied through dedicated control lines. However, these microwave pulses may also drive other qubits due to crosstalk arising from capacitive coupling and wavefunction overlap in systems with closely spaced transition frequencies. Crosstalk and frequency crowding increase errors during simultaneous single-qubit operations relative to isolated gates, thus forming a major bottleneck for scaling superconducting quantum processors. In this work, we combine model-based qubit frequency optimization with pulse shaping to demonstrate crosstalk error mitigation in single-qubit gates on a 49-qubit superconducting quantum processor. We introduce and experimentally verify an analytical model of simultaneous single-qubit gate error caused by microwave crosstalk that depends on a given pulse shape. By employing a model-based optimization strategy of qubit frequencies, we minimize the crosstalk-induced error across the processor and achieve a mean simultaneous single-qubit gate fidelity of 99.96% for a 16-ns gate duration, approaching the mean individual gate fidelity. To further reduce the simultaneous error and required qubit frequency bandwidth on high-crosstalk qubit pairs, we introduce a crosstalk transition suppression (CTS) pulse shaping technique that minimizes the spectral energy around transitions inducing leakage and crosstalk errors. Finally, we combine CTS with model-based frequency optimization across the device and experimentally show a systematic reduction in the required qubit frequency bandwidth for high-fidelity simultaneous gates, supported by simulations of systems with up to 1000 qubits. By alleviating constraints on qubit frequency bandwidth for parallel single-qubit operations, this work represents an important step for scaling towards larger quantum processors.
The possibility to utilize different types of two-qubit gates on a single quantum computing platform adds flexibility in the decomposition of quantum algorithms.A larger hardware-native gate set may decrease the number of required gates, provided that all gates are realized with high fidelity.Here, we benchmark both controlled-Z (CZ) and exchange-type (iSWAP) gates using a parametrically driven tunable coupler that mediates the interaction between two superconducting qubits.Using randomized benchmarking protocols we estimate an error per gate of 0.9 ± 0.03 and 1.3 ± 0.4% for the CZ and the iSWAP gate, respectively.We argue that spurious ZZ-type couplings are the dominant error source for the iSWAP gate, and that phase stability of all microwave drives is of utmost importance.Such differences in the achievable fidelities for different two-qubit gates have to be taken into account when mapping quantum algorithms to real hardware.
We present a simple, malleable and low-overhead approach for improving generic biased quantum error mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on 100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmark circuits which mirror the application circuit's native-gate structure and thus noise profile. These circuits can be used to benchmark and mitigate the bias of the underlying error mitigation method, requiring only the application circuit and hardware native gate set. We present two methods for generating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and has no gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE) as a simple adaptation of zero-noise extrapolation (ZNE), one of the most popular error mitigation methods. We consider as an example the bias-mitigated ZNE and bnZNE of Trotterized Hamiltonian simulations, observing that our approaches outperform standard ZNE using both small-scale classical simulations and 100-qubit utility-scale experiments on the IBM superconducting hardware. We consider the measurement of both single-site observables as well as two-site correlations along a one-dimensional qubit chain. We also provide a software package for implementing the error mitigation techniques used in this research.