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arXiv:2607.01422

High-Precision Calibration Workflow Achieves Above $99.9\%$ CZ Gate Fidelity on a Scalable Superconducting Processor

Huili Zhang, Meiling Li, Shuang Yang, Yaqing Feng, Yulong Li, Cheng Chen, Pei Liu, Guangming Xue, Haifeng Yu

quant-phSubmitted Jul 1, 2026• Announced Jul 3, 2026• 0 citations
arXivHTMLPDF

Abstract

High-fidelity universal two-qubit gates are critical for building fault-tolerant quantum computers. In scalable superconducting processors, shortened coherence times introduce more incoherent errors in gate operations. With a constrained error budget, there is reduced tolerance for coherent errors stemming from parameter deviations. In this work, we develop a closed-loop workflow to enhance the CZ gate calibration precision. Utilizing the echoed leakage error amplification (ELEA) and the repurposed context-aware fidelity estimation (CAFE) circuits, we suppress the population leakage to non-computational states, and, for the first time, demonstrate a CZ gate fidelity exceeding $99.9\%$ on an 84-qubit processor, with coherent error suppressed to $0.007\%$. Meanwhile, we obtain a median fidelity of $99.25\%$ among 72 CZ gates, demonstrating that the workflow can be generalized to the calibration of parallel CZ gates. Finally, we realize automated calibration and observe enhanced stability of the CZ gate throughout 9-hour comparative monitoring experiments. Our results, realized on a completely domestic platform, establish an efficient and automated route to quantum computation with superconducting quantum systems.

Comments
13 pages, 10 figures

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High-Precision Calibration Workflow Achieves Above 99.9%99.9\%99.9% CZ Gate Fidelity on a Scalable Superconducting Processor
High-fidelity universal two-qubit gates are critical for building fault-tolerant quantum computers. In scalable superconducting processors, shortened coherence times introduce more incoherent errors in gate operations. With a constrained error budget, there is reduced tolerance for coherent errors stemming from parameter deviations. In this work, we develop a closed-loop workflow to enhance the CZ gate calibration precision. Utilizing the echoed leakage error amplification (ELEA) and the repurposed context-aware fidelity estimation (CAFE) circuits, we suppress the population leakage to non-computational states, and, for the first time, demonstrate a CZ gate fidelity exceeding 99.9%99.9\%99.9% on an 84-qubit processor, with coherent error suppressed to 0.007%0.007\%0.007%. Meanwhile, we obtain a median fidelity of 99.25%99.25\%99.25% among 72 CZ gates, demonstrating that the workflow can be generalized to the calibration of parallel CZ gates. Finally, we realize automated calibration and observe enhanced stability of the CZ gate throughout 9-hour comparative monitoring experiments. Our results, realized on a completely domestic platform, establish an efficient and automated route to quantum computation with superconducting quantum systems.
Achieving high-fidelity single-qubit gates, two-qubit gates, and qubit readout is critical for building scalable, error-corrected quantum computers. However, device parameters that enhance one operation often degrade the others, making simultaneous optimization challenging. Here, we demonstrate that careful tuning of qubit-coupler coupling strengths in a superconducting circuit with two transmon qubits coupled via a tunable coupler enables high-fidelity single- and two-qubit gates, without compromising readout performance. Furthermore, we introduce a new calibration protocol for diabatic controlled- Z gates, phased-averaged leakage error amplification (PALEA), which enables efficient suppression of coherent gate errors and leakage to noncomputational states. Using PALEA in combination with careful tuning of qubit-coupler coupling strengths, we achieve a 40 h-averaged CZ gate fidelity of 99.93 %, simultaneous single-qubit gate fidelities of 99.98 %, and readout fidelities over 99.94 % in a single device. Our results demonstrate a viable path toward scaling up superconducting quantum processors while maintaining consistently high gate and readout fidelities.
As superconducting quantum processors scale toward hundreds of qubits, manual calibration becomes increasingly costly and difficult to sustain. Here we address two system-level factors governing automated calibration, namely, crosstalk induced by parallel operations and temporal drift of control parameters. On a 66-qubit superconducting processor, cross-entropy benchmarking shows that single-qubit calibration tolerates full-chip concurrency with minimal fidelity loss, whereas CZ calibration requires a minimum coupler-graph distance of four to avoid elevated control errors. Continuous monitoring of representative qubit and coupler parameters further yields quantitative refresh rules that assign refresh priority by error-budget consumption. These results turn two conventionally heuristic choices, the concurrency density of calibration tasks and the refresh priority of each control parameter, into measurable operating rules. Implemented within an automated calibration framework, the rules support a six-qubit Greenberger-Horne-Zeilinger state with a zero-noise-extrapolated fidelity of 89.64%, distance-dependent logical-error suppression in a single-cycle repetition-code benchmark, and a reduction of the mean single-qubit error from 0.023 to 0.011 on a 337-qubit processor, providing an experimentally grounded reference for the automated calibration and maintenance of current and future large-scale superconducting quantum systems.
High fidelity quantum operations are key to enabling fault-tolerant quantum computation. Superconducting quantum processors have demonstrated high-fidelity operations, but on larger devices there is commonly a broad distribution of qualities, with the low-performing tail affecting near-term performance and applications. Here we present an error budgeting procedure for the native two-qubit operation on a 32-qubit superconducting-qubit-based quantum computer, the OQC Toshiko gen-1 system. We estimate the prevalence of different forms of error such as coherent error and control qubit leakage, then apply error suppression strategies based on the most significant sources of error, making use of pulse-shaping and additional compensating gates. These techniques require no additional hardware overhead and little additional calibration, making them suitable for routine adoption. An average reduction of 3.7x in error rate for two qubit operations is shown across a chain of 16 qubits, with the median error rate improving from 4.6%\%% to 1.2%\%% as measured by interleaved randomized benchmarking. The largest improvements are seen on previously under-performing qubit pairs, demonstrating the importance of practical error suppression in reducing the low-performing tail of gate qualities and achieving consistently good performance across a device.
Quantum error correction imposes stringent requirements on the underlying hardware: all core operations of a quantum processor – single-qubit gates, two-qubit entangling gates, qubit readout, and qubit reset – must operate well below the error thresholds of leading codes. While such thresholds have already been crossed in several platforms, the associated overhead in physical qubits and circuit depth remains extremely sensitive to the physical error rate. This thesis investigates how far a superconducting platform based on transmon qubits can be pushed toward its physical limits, and how architectural and control choices can be optimized to reduce the overhead required for fault-tolerant quantum computation. First, we develop and characterize tunable-coupler architectures that enable fast, high-fidelity controlled-Z (CZ) gates. A long-distance coupler increases the qubit-qubit separation, freeing chip area for additional on-chip components, while still achieving CZ fidelities above 99.8%. Building on this, we optimize the qubit-coupler coupling to simultaneously support high-performance single- and two-qubit gates. We achieve simultaneous single- and two-qubit gate fidelities exceeding 99.9% on the same chip using a CZ calibration experiment based on our phase-averaged leakage error amplification (PALEA) protocol. PALEA coherently amplifies small over- and under-rotations of the diabatic CZ gate, making calibration errors easier to detect and correct. Second, we address single-qubit gates. Using spectrally engineered FAST-DRAG and higherderivative DRAG pulses, we demonstrate sub-8 ns gates with errors of order 10!" and strongly suppressed leakage. Third, we address readout by combining shelving to a higher qubit level with Purcell-filtered resonators and quantum-limited amplification, achieving readout errors below 10!#. Beyond the transmon workhorse, we explore the unimon qubit, which combines large anharmonicity with reduced charge sensitivity, and investigate a quantum circuit refrigerator as an integrated resource for fast, unconditional qubit reset via engineered dissipation. Finally, we demonstrate a cryogenic microwave link between two dilution refrigerators, enabling remote state transfer and entanglement over a five-meter distance and illustrating a path toward modular and distributed superconducting quantum processors. Together, these results show that with careful co-design of device layout, coupling topology, pulse shaping, and calibration protocols, all core operations – except qubit reset – of a superconducting quantum processor can be operated in the 10!#–10!" error regime within a coherent hardware and control stack, substantially lowering the resource overhead required for future fault-tolerant architectures.
High-fidelity quantum gates are essential for scalable quantum computation. However, at short durations, short-timescale waveform distortions break the time-reflection symmetry of control pulses, preventing the precise closure of cyclic evolution. This mechanism renders conventional symmetric protocols intrinsically over-constrained. Conventional strategies typically rely on smoothing the pulse envelopes or embedding the interaction pulse within a longer qubit pulse to bypass short-timescale distortions, which inevitably leads to a persistent speed-fidelity trade-off. To overcome this limitation, we introduce a cyclic control strategy based on parameter-space expansion, which restores controllability by incorporating an additional degree of freedom. We experimentally demonstrate this approach in a superconducting controlled-Z gate, achieving robust suppression of coherent errors without increasing gate duration, reducing the average coherent error from 0.27% to 0.12% across multiple two-qubit gates, as validated by cross-entropy benchmarking. Our results establish a general route to fast, high-fidelity cyclic quantum gates beyond the conventional speed-fidelity trade-off.
Creation and manipulation of entanglement with low error is essential in quantum information systems. In practice, two-qubit entangling gates constitute a dominant error source, limiting circuit depths and performance in fault-tolerant architectures. Using a neutral-atom quantum processor, we realize entangling CZ gates with a high Rabi frequency smooth-amplitude pulse, employing state-selective readout and qubit reuse for fast calibration, and achieve state-of-the-art fidelities of 99.854(4)% which improve to 99.941(3)% upon loss postselection, with stable performance for 10 hours. We then use these low-error gates in quantum circuits with coherent atom rearrangement. We first benchmark performance by creating and disentangling cluster states, and subsequently implement scrambling circuits featuring longer-range connectivity to study non-locally entangled states generated through chaotic dynamics. These results pave the way towards deep-circuit, efficient fault-tolerant quantum computation.