Echo Cross Resonance gate error budgeting on a superconducting quantum processor
Travers Ward, Russell P. Rundle, Richard Bounds, Norbert Deak, Gavin Dold, Apoorva Hegde, William Howard, Ailsa Keyser, George B. Long, Benjamin Rogers, Jonathan J. Burnett, Bryn A. Bell
quant-phSubmitted Jan 28, 2026• Announced Jan 29, 2026• 0 citations
High fidelity quantum operations are key to enabling fault-tolerant quantum computation. Superconducting quantum processors have demonstrated high-fidelity operations, but on larger devices there is commonly a broad distribution of qualities, with the low-performing tail affecting near-term performance and applications. Here we present an error budgeting procedure for the native two-qubit operation on a 32-qubit superconducting-qubit-based quantum computer, the OQC Toshiko gen-1 system. We estimate the prevalence of different forms of error such as coherent error and control qubit leakage, then apply error suppression strategies based on the most significant sources of error, making use of pulse-shaping and additional compensating gates. These techniques require no additional hardware overhead and little additional calibration, making them suitable for routine adoption. An average reduction of 3.7x in error rate for two qubit operations is shown across a chain of 16 qubits, with the median error rate improving from 4.6$\%$ to 1.2$\%$ as measured by interleaved randomized benchmarking. The largest improvements are seen on previously under-performing qubit pairs, demonstrating the importance of practical error suppression in reducing the low-performing tail of gate qualities and achieving consistently good performance across a device.
High fidelity quantum operations are key to enabling fault-tolerant quantum computation. Superconducting quantum processors have demonstrated high-fidelity operations, but on larger devices there is commonly a broad distribution of qualities, with the low-performing tail affecting near-term performance and applications. Here we present an error budgeting procedure for the native two-qubit operation on a 32-qubit superconducting-qubit-based quantum computer, the OQC Toshiko gen-1 system. We estimate the prevalence of different forms of error such as coherent error and control qubit leakage, then apply error suppression strategies based on the most significant sources of error, making use of pulse-shaping and additional compensating gates. These techniques require no additional hardware overhead and little additional calibration, making them suitable for routine adoption. An average reduction of 3.7x in error rate for two qubit operations is shown across a chain of 16 qubits, with the median error rate improving from 4.6% to 1.2% as measured by interleaved randomized benchmarking. The largest improvements are seen on previously under-performing qubit pairs, demonstrating the importance of practical error suppression in reducing the low-performing tail of gate qualities and achieving consistently good performance across a device.
Single-qubit gates on superconducting quantum processors are typically implemented using microwave pulses applied through dedicated control lines. However, these microwave pulses may also drive other qubits due to crosstalk arising from capacitive coupling and wavefunction overlap in systems with closely spaced transition frequencies. Crosstalk and frequency crowding increase errors during simultaneous single-qubit operations relative to isolated gates, thus forming a major bottleneck for scaling superconducting quantum processors. In this work, we combine model-based qubit frequency optimization with pulse shaping to demonstrate crosstalk error mitigation in single-qubit gates on a 49-qubit superconducting quantum processor. We introduce and experimentally verify an analytical model of simultaneous single-qubit gate error caused by microwave crosstalk that depends on a given pulse shape. By employing a model-based optimization strategy of qubit frequencies, we minimize the crosstalk-induced error across the processor and achieve a mean simultaneous single-qubit gate fidelity of 99.96% for a 16-ns gate duration, approaching the mean individual gate fidelity. To further reduce the simultaneous error and required qubit frequency bandwidth on high-crosstalk qubit pairs, we introduce a crosstalk transition suppression (CTS) pulse shaping technique that minimizes the spectral energy around transitions inducing leakage and crosstalk errors. Finally, we combine CTS with model-based frequency optimization across the device and experimentally show a systematic reduction in the required qubit frequency bandwidth for high-fidelity simultaneous gates, supported by simulations of systems with up to 1000 qubits. By alleviating constraints on qubit frequency bandwidth for parallel single-qubit operations, this work represents an important step for scaling towards larger quantum processors.
Quantum error correction imposes stringent requirements on the underlying hardware: all core operations of a quantum processor – single-qubit gates, two-qubit entangling gates, qubit readout, and qubit reset – must operate well below the error thresholds of leading codes. While such thresholds have already been crossed in several platforms, the associated overhead in physical qubits and circuit depth remains extremely sensitive to the physical error rate. This thesis investigates how far a superconducting platform based on transmon qubits can be pushed toward its physical limits, and how architectural and control choices can be optimized to reduce the overhead required for fault-tolerant quantum computation. First, we develop and characterize tunable-coupler architectures that enable fast, high-fidelity controlled-Z (CZ) gates. A long-distance coupler increases the qubit-qubit separation, freeing chip area for additional on-chip components, while still achieving CZ fidelities above 99.8%. Building on this, we optimize the qubit-coupler coupling to simultaneously support high-performance single- and two-qubit gates. We achieve simultaneous single- and two-qubit gate fidelities exceeding 99.9% on the same chip using a CZ calibration experiment based on our phase-averaged leakage error amplification (PALEA) protocol. PALEA coherently amplifies small over- and under-rotations of the diabatic CZ gate, making calibration errors easier to detect and correct. Second, we address single-qubit gates. Using spectrally engineered FAST-DRAG and higherderivative DRAG pulses, we demonstrate sub-8 ns gates with errors of order 10!" and strongly suppressed leakage. Third, we address readout by combining shelving to a higher qubit level with Purcell-filtered resonators and quantum-limited amplification, achieving readout errors below 10!#. Beyond the transmon workhorse, we explore the unimon qubit, which combines large anharmonicity with reduced charge sensitivity, and investigate a quantum circuit refrigerator as an integrated resource for fast, unconditional qubit reset via engineered dissipation. Finally, we demonstrate a cryogenic microwave link between two dilution refrigerators, enabling remote state transfer and entanglement over a five-meter distance and illustrating a path toward modular and distributed superconducting quantum processors. Together, these results show that with careful co-design of device layout, coupling topology, pulse shaping, and calibration protocols, all core operations – except qubit reset – of a superconducting quantum processor can be operated in the 10!#–10!" error regime within a coherent hardware and control stack, substantially lowering the resource overhead required for future fault-tolerant architectures.
Large quantum computations require high-fidelity error-corrected memory and fault-tolerant logical operations. To achieve these with superconducting circuits, quantum processors will need many components operating with low error rates. In practice, fabrication of monolithic superconducting devices produces unavoidable heterogeneity in component performance, which the quantum computer must accommodate. We implement strategies to operate a large dynamic compass code on an array of 156 superconducting qubits arranged on a heavy-hexagonal lattice, making use of the entire monolithic quantum processor and redesigning our measurement schedule to exclude underperforming components. We demonstrate improvements of up to 35% in logical error probabilities for a memory experiment by using a noise-informed decoder combined with strategies to exclude the worst-performing qubits and couplers, along with post-selecting on shots with a low probability of leakage errors. In addition to these memory results, we also observe performance gains of up to 56% when these strategies are applied to measurement-based logic, demonstrated by stability experiments. We furthermore demonstrate high-fidelity fault-tolerant logic through lattice surgery. Through pre-selection filtering techniques, we can obtain Bell fidelities above 77%, and further logical gap post-selection using exclusive decoding increases these fidelities to above 97%. Our experiments demonstrate that high performance can be maintained in key elements of fault-tolerant quantum memory and logic when working on monolithic superconducting quantum processors with underperforming components, by using a suite of noise-informed quantum error correction strategies.
Quantum computing promises to address problems in simulation, optimization, and chemistry, but current hardware operates in the noisy intermediate-scale (NISQ) regime where coherence limits, gate imperfections, and readout errors restrict performance. Improving calibration and mitigating errors therefore remain essential. This thesis analyzes error reduction on superconducting transmon qubits through calibration, gate analysis, and circuit-level mitigation. It compares single-qubit amplitude calibration methods and analyzes two-qubit gates based on the cross-resonance interaction, identifying differences in precision, convergence, and performance. In addition, it develops Inverted-Circuit Zero-Noise-Extrapolation (IC-ZNE) which measures effective error strength using inverted circuits. Compared to standard ZNE, IC-ZNE achieves results closer to ideal values and reduces observable errors. Overall, the presented methods improve the reliability of near-term quantum processors.
High-quality two-qubit gate operations are crucial for scalable quantum information processing. Often, the gate fidelity is compromised when the system becomes more integrated. Therefore, a low-error-rate, easy-to-scale two-qubit gate scheme is highly desirable. Here, we experimentally demonstrate a new two-qubit gate scheme that exploits fixed-frequency qubits and a tunable coupler in a superconducting quantum circuit. The scheme requires less control lines, reduces cross talk effect, and simplifies calibration procedures, yet produces a controlled-Z gate in 30 ns with a high fidelity of 99.5%, derived from the interleaved randomized benchmarking method. Error analysis shows that gate errors are mostly coherence limited. Our demonstration paves the way for large-scale implementation of high-fidelity quantum operations.
Maintaining or even improving gate performance with growing numbers of parallel controlled qubits is a vital requirement for fault-tolerant quantum computing.For superconducting quantum processors, though isolated one-or two-qubit gates have been demonstrated with high fidelity, implementing these gates in parallel commonly shows worse performance.Generally, this degradation is attributed to various crosstalks between qubits, such as quantum crosstalk due to residual inter-qubit coupling.An understanding of the exact nature of these crosstalks is critical to figuring out respective mitigation schemes and improved qubit architecture designs with low crosstalk.Here we give a theoretical analysis of quantum crosstalk impact on simultaneous gate operations in a qubit architecture, where fixed-frequency transmon qubits are coupled via a tunable bus, and sub-100-ns controlled-Z (CZ) gates can be realized by applying a baseband flux pulse on the bus.Our analysis shows that for microwave-driven single-qubit gates, the dressing from the qubit-qubit coupling can cause non-negligible cross-driving errors when qubits operate near frequency collision regions.During CZ gate operations, although unwanted nearest-neighbor interactions are nominally turned off, sub-MHz parasitic next-nearest-neighbor interactions involving spectator qubits can still exist, causing considerable leakage or control error when one operates qubit systems around these parasitic resonance points.To ensure high-fidelity simultaneous operations, a request could be raised to figure out a better way to balance the gate error from target qubit systems themselves and the error from nonparticipating spectator qubits.Overall, our analysis suggests that towards useful quantum processors, the qubit architecture should be examined carefully in the context of high-fidelity simultaneous gate operations in a scalable qubit lattice.