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Huipputason ydinoperaatiot suprajohtavissa kvanttiprosessoreissa

Fabian Marxer

Published Jan 1, 2026• 0 citations
OpenAlex

Abstract

Quantum error correction imposes stringent requirements on the underlying hardware: all core operations of a quantum processor – single-qubit gates, two-qubit entangling gates, qubit readout, and qubit reset – must operate well below the error thresholds of leading codes. While such thresholds have already been crossed in several platforms, the associated overhead in physical qubits and circuit depth remains extremely sensitive to the physical error rate. This thesis investigates how far a superconducting platform based on transmon qubits can be pushed toward its physical limits, and how architectural and control choices can be optimized to reduce the overhead required for fault-tolerant quantum computation. First, we develop and characterize tunable-coupler architectures that enable fast, high-fidelity controlled-Z (CZ) gates. A long-distance coupler increases the qubit-qubit separation, freeing chip area for additional on-chip components, while still achieving CZ fidelities above 99.8%. Building on this, we optimize the qubit-coupler coupling to simultaneously support high-performance single- and two-qubit gates. We achieve simultaneous single- and two-qubit gate fidelities exceeding 99.9% on the same chip using a CZ calibration experiment based on our phase-averaged leakage error amplification (PALEA) protocol. PALEA coherently amplifies small over- and under-rotations of the diabatic CZ gate, making calibration errors easier to detect and correct. Second, we address single-qubit gates. Using spectrally engineered FAST-DRAG and higherderivative DRAG pulses, we demonstrate sub-8 ns gates with errors of order 10!" and strongly suppressed leakage. Third, we address readout by combining shelving to a higher qubit level with Purcell-filtered resonators and quantum-limited amplification, achieving readout errors below 10!#. Beyond the transmon workhorse, we explore the unimon qubit, which combines large anharmonicity with reduced charge sensitivity, and investigate a quantum circuit refrigerator as an integrated resource for fast, unconditional qubit reset via engineered dissipation. Finally, we demonstrate a cryogenic microwave link between two dilution refrigerators, enabling remote state transfer and entanglement over a five-meter distance and illustrating a path toward modular and distributed superconducting quantum processors. Together, these results show that with careful co-design of device layout, coupling topology, pulse shaping, and calibration protocols, all core operations – except qubit reset – of a superconducting quantum processor can be operated in the 10!#–10!" error regime within a coherent hardware and control stack, substantially lowering the resource overhead required for future fault-tolerant architectures.

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The discovery of quantum mechanics in the 20th century forms the basis of many of the technologies that define our lives today. The ability to engineer and manipulate individual quantum systems -- even create artificial atoms -- promises a similar revolutionary leap in technology. A quantum technology of particular interest is quantum computing, which has the potential to solve problems that are intractable for classical computers, opening up new domains of computation. Meanwhile, an attractive approach to creating engineered quantum systems is circuit quantum electrodynamics (cQED). Where research initially focused on understanding the physics of cQED devices, focus has shifted to building systems capable of performing useful computations. However, this remains extremely challenging, in part due to the inherently fragile nature of the individual quantum bits, but also due to difficulties in controlling and scaling up these systems. This thesis focuses on the control aspects of building an extensible full-stack quantum computer based on superconducting transmon qubits. We define the demonstration of quantum fault-tolerance as our target application to give focus to our efforts. The QuSurf architecture for a full-stack quantum computer presented in this thesis is designed with this application in mind. We provide a detailed study of the error sources present in this system and give an overview of the relevant characterization techniques. In the second part of this thesis, we address several key challenges in the control of a quantum computer. To realize high-fidelity coherence limited gates, we present a novel tuneup protocol that achieves a tenfold speedup over the state-of-the-art. This is realized by eliminating the need for qubit initialization. We demonstrate this protocol by calibrating single-qubit gates to a coherence limited Clifford fidelity of 99.9% in one minute. Performing repeated parity checks, as is required for quantum error correction, requires reusing qubits quickly after they have been measured. By introducing a numerically optimized depletion pulse we are able to speeds up the depletion of measurement photons in a readout resonator without having to rely on specific symmetry conditions. Using this technique speed up photon depletion by more than six inverse resonator linewidths, reducing the error rate in an emulated ancilla parity check by a factor 75. Flux-pulsing based two-qubit gates are the fastest two-qubit gates. However, they are also very technically demanding. The key challenge in performing these gates is addressing the distortions that control signals experience as they traverse various electrical components. We have developed Cryoscope (short for cryogenic oscilloscope) to characterize and correct these distortions. Cryoscope is an in-situ technique that uses the qubit to sample control pulses of arbitrary shape. Even when correcting distortions to within $\\sim 0.1\\%$ two-qubit gates are history-dependent due to the long timescale upon which some of these distortions act. We have invented Net-Zero, a new type of flux-pulsing based two-qubit gate, to address this problem. It makes use of a symmetry condition of the transmon to have net-zero integral, making the gate resilient to long-timescale distortions. The gate suppresses leakage out of the computational subspace to 0.1% by making use of leakage interference and has a built-in echo effect that enhances the coherence of the gate, achieving a two-qubit gate fidelity of 99.1%. Custom software is required to perform the physics experiments needed to build and operate a quantum computer. PycQED is an open-source software framework we have developed for this purpose. We discuss the design choices and concepts of PycQED before turning our focus to characterization and calibration. Here we introduced dependency graphs as a useful abstraction and system emulation as an essential development tool for automating the characterization and calibration process. We conclude the thesis by reflecting on the limitations of our architecture and providing an outlook on the grand challenges of building a useful kilo-qubit sized quantum computer. We define these challenges as The Application Problem, The Fabrication Problem, and The Calibration Problem.

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Quantum error correction imposes stringent requirements on the underlying hardware: all core operations of a quantum processor – single-qubit gates, two-qubit entangling gates, qubit readout, and qubit reset – must operate well below the error thresholds of leading codes. While such thresholds have already been crossed in several platforms, the associated overhead in physical qubits and circuit depth remains extremely sensitive to the physical error rate. This thesis investigates how far a superconducting platform based on transmon qubits can be pushed toward its physical limits, and how architectural and control choices can be optimized to reduce the overhead required for fault-tolerant quantum computation. First, we develop and characterize tunable-coupler architectures that enable fast, high-fidelity controlled-Z (CZ) gates. A long-distance coupler increases the qubit-qubit separation, freeing chip area for additional on-chip components, while still achieving CZ fidelities above 99.8%. Building on this, we optimize the qubit-coupler coupling to simultaneously support high-performance single- and two-qubit gates. We achieve simultaneous single- and two-qubit gate fidelities exceeding 99.9% on the same chip using a CZ calibration experiment based on our phase-averaged leakage error amplification (PALEA) protocol. PALEA coherently amplifies small over- and under-rotations of the diabatic CZ gate, making calibration errors easier to detect and correct. Second, we address single-qubit gates. Using spectrally engineered FAST-DRAG and higherderivative DRAG pulses, we demonstrate sub-8 ns gates with errors of order 10!" and strongly suppressed leakage. Third, we address readout by combining shelving to a higher qubit level with Purcell-filtered resonators and quantum-limited amplification, achieving readout errors below 10!#. Beyond the transmon workhorse, we explore the unimon qubit, which combines large anharmonicity with reduced charge sensitivity, and investigate a quantum circuit refrigerator as an integrated resource for fast, unconditional qubit reset via engineered dissipation. Finally, we demonstrate a cryogenic microwave link between two dilution refrigerators, enabling remote state transfer and entanglement over a five-meter distance and illustrating a path toward modular and distributed superconducting quantum processors. Together, these results show that with careful co-design of device layout, coupling topology, pulse shaping, and calibration protocols, all core operations – except qubit reset – of a superconducting quantum processor can be operated in the 10!#–10!" error regime within a coherent hardware and control stack, substantially lowering the resource overhead required for future fault-tolerant architectures.
Achieving high-fidelity single-qubit gates, two-qubit gates, and qubit readout is critical for building scalable, error-corrected quantum computers. However, device parameters that enhance one operation often degrade the others, making simultaneous optimization challenging. Here, we demonstrate that careful tuning of qubit-coupler coupling strengths in a superconducting circuit with two transmon qubits coupled via a tunable coupler enables high-fidelity single- and two-qubit gates, without compromising readout performance. Furthermore, we introduce a new calibration protocol for diabatic controlled- Z gates, phased-averaged leakage error amplification (PALEA), which enables efficient suppression of coherent gate errors and leakage to noncomputational states. Using PALEA in combination with careful tuning of qubit-coupler coupling strengths, we achieve a 40 h-averaged CZ gate fidelity of 99.93 %, simultaneous single-qubit gate fidelities of 99.98 %, and readout fidelities over 99.94 % in a single device. Our results demonstrate a viable path toward scaling up superconducting quantum processors while maintaining consistently high gate and readout fidelities.
The realization of fault-tolerant quantum computing requires the execution of quantum error-correction (QEC) schemes, to mitigate the fragile nature of qubits. In this context, to ensure the success of QEC, a protocol capable of implementing both qubit reset and leakage reduction is highly desirable together with the ability to perform fast and high-fidelity readout of the qubit s’ quantum states. In this thesis, we tackle both these challenges in an architecture consisting of fixed-frequency transmon qubits pair-wise coupled via tunable couplers. We demonstrate a readout scheme that combines two microwave techniques: applying a shelving technique to the qubits that reduces the contribution of decay error during readout, and a two-tone excitation of the readout resonators to distinguish among qubits’ populations in higher energy levels. We perform single-shot frequency-multiplexed qubit readout, with a 140 ns readout time, and demonstrate 99.5% assignment fidelity for two-state readout and 96.9% for three-state readout - without using a quantum-limited amplifier. We also demonstrate a reset scheme that is fast, unconditional, and achieves fidelities well above 99%, thus enabling fixed-frequency qubit architectures as future implementations of fault-tolerant quantum computers. Our reset protocol uses the tunable couplers to transfer any undesired qubits’ excitation to the readout resonators of the qubits, from which this excitation decays into the feedline. In total, the combination of qubit reset, leakage reduction, and coupler reset takes only 83 ns to complete. This reset protocol also provides a means to both reduce QEC cycle runtime and improve algorithmic fidelity on quantum processors.
This thesis explores novel strategies for advancing superconducting quantum computing through a series of experimental investigations and device innovations. Grounded in the development of circuit quantum electrodynamics, the work addresses the challenges posed by the limitations of coherent control, coherence time and scaling of superconducting qubits. Focusing on transmon qubits, the thesis first reviews the foundational principles of circuit quantum electrodynamics and the critical role of the transmon in achieving robust qubit performance. Three experimental studies form the core of this work. The first study demonstrates a universal quantum gate set for strongly coupled transmons. By exploiting the residual ZZ interaction, the work introduces a novel two-axis gate protocol for single-qubit operations and implements both CZ and CNOT gates with high fidelities, highlighting the potential for fast, low-error quantum operations in the strong coupling regime. The second study investigates a dual-rail qubit architecture using parametrically coupled transmons, showcasing a hardware-efficient approach to quantum error correction. This experiment converts single-photon loss errors into detectable erasures and leverages mid-circuit detection to enhance qubit coherence, thereby advancing fault-tolerant quantum computing schemes in the NISQ era. The final study focuses on the development of merged-element transmons (MET) and their FinMET variants. By integrating the Josephson junction and shunt capacitor into a single trilayer device, these innovations achieve a dramatic reduction in device footprint while addressing loss channels through advanced materials engineering, ultimately paving the way for scalable, high-coherence quantum circuits. Collectively, these contributions demonstrate significant progress in quantum gate design, error mitigation, and qubit architecture, offering promising routes toward the realization of largescale, fault-tolerant quantum computers
Fault-tolerant quantum computing requires quantum gates that combine short duration, high fidelity, and robustness to noise. As quantum processors scale, robustness becomes increasingly important because exhaustive characterization and frequent recalibration of individual gates become impractical. We present a comprehensive optimal-control framework for controlled-Z (CZ) gates between directly coupled, frequency-tunable transmons that systematically accounts for intrinsic Hamiltonian errors and realistic decoherence mechanisms, including energy relaxation and dephasing. Using smooth, single-shot flux pulses, we obtain 12-ns CZ gates---close to the theoretical speed limit of 11.6 ns---with intrinsic errors suppressed to the 2×10−52\times10^{-5}2×10−5 level. We construct dephasing noise models, calibrated against published experimental measurements, that capture fast dephasing from room-temperature control electronics and slow dephasing from 1/f1/f1/f flux noise. Using these models, we identify dephasing sweet spots that suppress sensitivity to dephasing noise. We further exploit transmon asymmetry as a design parameter to access distinct noise-resilient operating regimes. These results establish an experimentally applicable framework for balancing gate speed, fidelity, and noise robustness while reducing characterization and recalibration overhead.
The discovery of quantum mechanics in the 20th century forms the basis of many of the technologies that define our lives today. The ability to engineer and manipulate individual quantum systems -- even create artificial atoms -- promises a similar revolutionary leap in technology. A quantum technology of particular interest is quantum computing, which has the potential to solve problems that are intractable for classical computers, opening up new domains of computation. Meanwhile, an attractive approach to creating engineered quantum systems is circuit quantum electrodynamics (cQED). Where research initially focused on understanding the physics of cQED devices, focus has shifted to building systems capable of performing useful computations. However, this remains extremely challenging, in part due to the inherently fragile nature of the individual quantum bits, but also due to difficulties in controlling and scaling up these systems. This thesis focuses on the control aspects of building an extensible full-stack quantum computer based on superconducting transmon qubits. We define the demonstration of quantum fault-tolerance as our target application to give focus to our efforts. The QuSurf architecture for a full-stack quantum computer presented in this thesis is designed with this application in mind. We provide a detailed study of the error sources present in this system and give an overview of the relevant characterization techniques. In the second part of this thesis, we address several key challenges in the control of a quantum computer. To realize high-fidelity coherence limited gates, we present a novel tuneup protocol that achieves a tenfold speedup over the state-of-the-art. This is realized by eliminating the need for qubit initialization. We demonstrate this protocol by calibrating single-qubit gates to a coherence limited Clifford fidelity of 99.9% in one minute. Performing repeated parity checks, as is required for quantum error correction, requires reusing qubits quickly after they have been measured. By introducing a numerically optimized depletion pulse we are able to speeds up the depletion of measurement photons in a readout resonator without having to rely on specific symmetry conditions. Using this technique speed up photon depletion by more than six inverse resonator linewidths, reducing the error rate in an emulated ancilla parity check by a factor 75. Flux-pulsing based two-qubit gates are the fastest two-qubit gates. However, they are also very technically demanding. The key challenge in performing these gates is addressing the distortions that control signals experience as they traverse various electrical components. We have developed Cryoscope (short for cryogenic oscilloscope) to characterize and correct these distortions. Cryoscope is an in-situ technique that uses the qubit to sample control pulses of arbitrary shape. Even when correcting distortions to within sim0.1\\sim 0.1\\%sim0.1 two-qubit gates are history-dependent due to the long timescale upon which some of these distortions act. We have invented Net-Zero, a new type of flux-pulsing based two-qubit gate, to address this problem. It makes use of a symmetry condition of the transmon to have net-zero integral, making the gate resilient to long-timescale distortions. The gate suppresses leakage out of the computational subspace to 0.1% by making use of leakage interference and has a built-in echo effect that enhances the coherence of the gate, achieving a two-qubit gate fidelity of 99.1%. Custom software is required to perform the physics experiments needed to build and operate a quantum computer. PycQED is an open-source software framework we have developed for this purpose. We discuss the design choices and concepts of PycQED before turning our focus to characterization and calibration. Here we introduced dependency graphs as a useful abstraction and system emulation as an essential development tool for automating the characterization and calibration process. We conclude the thesis by reflecting on the limitations of our architecture and providing an outlook on the grand challenges of building a useful kilo-qubit sized quantum computer. We define these challenges as The Application Problem, The Fabrication Problem, and The Calibration Problem.
High fidelity quantum operations are key to enabling fault-tolerant quantum computation. Superconducting quantum processors have demonstrated high-fidelity operations, but on larger devices there is commonly a broad distribution of qualities, with the low-performing tail affecting near-term performance and applications. Here we present an error budgeting procedure for the native two-qubit operation on a 32-qubit superconducting-qubit-based quantum computer, the OQC Toshiko gen-1 system. We estimate the prevalence of different forms of error such as coherent error and control qubit leakage, then apply error suppression strategies based on the most significant sources of error, making use of pulse-shaping and additional compensating gates. These techniques require no additional hardware overhead and little additional calibration, making them suitable for routine adoption. An average reduction of 3.7x in error rate for two qubit operations is shown across a chain of 16 qubits, with the median error rate improving from 4.6%\%% to 1.2%\%% as measured by interleaved randomized benchmarking. The largest improvements are seen on previously under-performing qubit pairs, demonstrating the importance of practical error suppression in reducing the low-performing tail of gate qualities and achieving consistently good performance across a device.