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arXiv:2510.16915 · IEEE Transactions on Quantum Engineering

Parameter Analysis and Optimization of Layer Fidelity for Quantum Processor Benchmarking at Scale

Maria Jose Lozano Palacio, Hasan M. Nayfeh, Matthew Ware, David C. McKay

Published Jan 1, 2026• 0 citations
arXivHTMLPDF

Abstract

With the continued scaling of quantum processors, holistic benchmarks are essential for extensively evaluating device performance. Layer fidelity is a benchmark well-suited to assessing processor performance at scale. Key advantages of this benchmark include its natural alignment with randomized benchmarking (RB) procedures, crosstalk awareness, fast measurements over large numbers of qubits, high signal-to-noise ratio, and fine-grained information [1]. In this work, we extend the analysis of the original layer fidelity manuscript to optimize parameters of the benchmark and extract deeper insights of its application. We present a robust protocol for identifying optimal qubit chains of arbitrary length$N$, demonstrating that our method yields error per layered gate (EPLG) values$40 \% - 70 \%$lower than randomly selected chains for$N=100$qubits. We further establish layer fidelity as an effective performance monitoring tool, capturing both edge-localized and device-wide degradation by tracking optimal chains of length 50 and 100, and fixed chains of length 100. Additionally, we refine error analysis by proposing parameter bounds on the number of randomizations and Clifford lengths used in direct RB fits, minimizing fit uncertainties. Finally, we use layer fidelity to analyze the impact of varying gate durations on layered two-qubit (2Q) errors, showing that prolonged gate times leading to idling times significantly increase these quantities. These findings extend the applicability of the layer fidelity benchmark and provide practical guidelines for optimizing quantum processor evaluations.

DOI
10.1109/tqe.2026.3668098

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With the continued scaling of quantum processors, holistic benchmarks are essential for extensively evaluating device performance. Layer fidelity is a benchmark well-suited to assessing processor performance at scale. Key advantages of this benchmark include its natural alignment with randomized benchmarking (RB) procedures, crosstalk awareness, fast measurements over large numbers of qubits, high signal-to-noise ratio, and fine-grained information [1]. In this work, we extend the analysis of the original layer fidelity manuscript to optimize parameters of the benchmark and extract deeper insights of its application. We present a robust protocol for identifying optimal qubit chains of arbitrary lengthNNN, demonstrating that our method yields error per layered gate (EPLG) values40%−70%40 \% - 70 \%40%−70%lower than randomly selected chains forN=100N=100N=100qubits. We further establish layer fidelity as an effective performance monitoring tool, capturing both edge-localized and device-wide degradation by tracking optimal chains of length 50 and 100, and fixed chains of length 100. Additionally, we refine error analysis by proposing parameter bounds on the number of randomizations and Clifford lengths used in direct RB fits, minimizing fit uncertainties. Finally, we use layer fidelity to analyze the impact of varying gate durations on layered two-qubit (2Q) errors, showing that prolonged gate times leading to idling times significantly increase these quantities. These findings extend the applicability of the layer fidelity benchmark and provide practical guidelines for optimizing quantum processor evaluations.
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Quantum computers have now surpassed classical simulation limits, yet noise continues to limit their practical utility. As the field shifts from proof-of-principle demonstrations to early deployments, there is no standard method for meaningfully and scalably comparing heterogeneous quantum hardware. Existing benchmarks typically focus on gate-level fidelity or constant-depth circuits, offering limited insight into algorithmic performance at depth. Here we introduce a benchmarking protocol based on the linear ramp quantum approximate optimization algorithm (LR-QAOA), a fixed-parameter, deterministic variant of QAOA. LR-QAOA quantifies a QPU's ability to preserve a coherent signal as circuit depth increases, identifying when performance becomes statistically indistinguishable from random sampling. We apply this protocol to 24 quantum processors from six vendors, testing problems with up to 156 qubits and 10,000 layers across 1D-chains, native layouts, and fully connected topologies. This constitutes the most extensive cross-platform quantum benchmarking effort to date, with circuits reaching a million two-qubit gates. LR-QAOA offers a scalable, unified benchmark across platforms and architectures, making it a tool for tracking performance in quantum computing.
Quantum computers have the potential to bring about a new age of technology, but in order for them to become a reality, the elephant in the room must be addressed, quantum errors. The complexity of quantum errors grows exponentially as the system size is increased; scalable characterization protocols which work under physically realistic noise are therefore needed to assess and optimize control. \n \nRandomized Benchmarking (RB) is a family of characterization protocols with the requisite qualities. RB protocols are independent of state preparation and measurement (SPAM) errors, and because they extract partial information about the error profiles in the form of figures of merit, they are scalable in the number of qubits. In this thesis, we study these figures of merit under various error models, gate-sets, and sample distributions, to further our understanding of their physical meaning, and to fine-tune the best practice for diagnosing errors in basic gate-sets. \n \nThe first study presented in this thesis looks at the physical meaning of the unitarity under physically realistic gate-dependent noise. Numerically, we demonstrate that under these realistic noise models, the unitarity obtained via Extended RB (XRB) overlaps strongly with the average of the unitarity of the errors over the set of individual operations. \n \nThe second study numerically and analytically proves that the Standard RB (SRB) decay parameter p coincides with the decay parameter of the novel figure of merit gate-set circuit fidelity. We also prove that, in the limit of high-fidelity single-qubit experiments, the disconnect between the average gate fidelity and SRB experimental results is caused by a basis mismatch between the gates and the state-preparation and measurement procedures. \n \nIn the third part of this thesis, we compare the results of two variations of the SRB protocol, one that samples uniformly (SRB) and one that samples non-uniformly (NIST RB) from the Clifford group. We prove that NIST RB produces an exponential fidelity curve that gives different infidelity results than SRB. \n \nThe fourth and final study gives a standard for assessing basic gate-sets. Experimental results are given from the assessment run on super-conducting and ion-trap devices. We also experimentally show how the systematic error bounds can be tightened by accounting for the error's degree of coherence, as well as using weaker randomizing sets.
Randomized benchmarking (RB) is a widely used method for estimating the average fidelity of gates implemented on a quantum computing device. The stochastic error of the average gate fidelity estimated by RB depends on the sampling strategy (i.e., how to sample sequences to be run in the protocol). The sampling strategy is determined by a set of configurable parameters (an RB configuration) that includes Clifford lengths (a list of the number of independent Clifford gates in a sequence) and the number of sequences for each Clifford length. The RB configuration is often chosen heuristically and there has been little research on its best configuration. Therefore, we propose a method for fully optimizing an RB configuration so that the confidence interval of the estimated fidelity is minimized while not increasing the total execution time of sequences. By experiments on real devices, we demonstrate the efficacy of the optimization method against heuristic selection in reducing the variance of the estimated fidelity.
Abstract Benchmarking large-scale quantum gates, typically involving multiple native two-qubit and single-qubit gates, is crucial in quantum computing. Global fidelity, encompassing information about inter-gate correlations, offers a comprehensive metric for evaluating and optimizing gate performance, unlike the fidelities of individual local native gates. In this work, utilizing the character-average benchmarking protocol implementable in a shallow circuit, we successfully benchmark gate fidelities up to 52 qubits. Notably, we achieved a fidelity of 63.09% ± 0.23% for a 44-qubit parallel CZ gate. Utilizing the global fidelity of the parallel CZ gate, we explore the correlations among local CZ gates by introducing an inter-gate correlation metric, enabling one to simultaneously quantify crosstalk error when benchmarking gate fidelity. Finally, we apply our methods in gate optimization. By leveraging global fidelity for optimization, we enhance the fidelity of a 6-qubit parallel CZ gate from 87.65% to 92.04% and decrease the gate correlation from 3.53% to 3.22%, compared to local gate fidelity-based optimization. The experimental results align well with our established composite noise model, incorporating depolarizing and Z Z-coupling noises, and provide valuable insight into further study and mitigation of correlated noise.
Benchmarking methods that can be adapted to multiqubit systems are essential for assessing the overall or "holistic" performance of nascent quantum processors. The current industry standard is Clifford randomized benchmarking (RB), which measures a single error rate that quantifies overall performance. But, scaling Clifford RB to many qubits is surprisingly hard. It has only been performed on one, two, and three qubits as of this writing. This reflects a fundamental inefficiency in Clifford RB: the n-qubit Clifford gates at its core have to be compiled into large circuits over the one- and two-qubit gates native to a device. As n grows, the quality of these Clifford gates quickly degrades, making Clifford RB impractical at relatively low n. In this Letter, we propose a direct RB protocol that mostly avoids compiling. Instead, it uses random circuits over the native gates in a device, which are seeded by an initial layer of Clifford-like randomization. We demonstrate this protocol experimentally on two to five qubits using the publicly available ibmqx5. We believe this to be the greatest number of qubits holistically benchmarked, and this was achieved on a freely available device without any special tuning up. Our protocol retains the simplicity and convenient properties of Clifford RB: it estimates an error rate from an exponential decay. But, it can be extended to processors with more qubits-we present simulations on 10+ qubits-and it reports a more directly informative and flexible error rate than the one reported by Clifford RB. We show how to use this flexibility to measure separate error rates for distinct sets of gates, and we use this method to estimate the average error rate of a set of cnot gates.