We propose and validate on real quantum computing hardware a new method for extended two-qubit gate set design, replacing iterative, fine calibration with fast characterization of a small number of gate parameters which are then tracked and corrected in circuit compilation. Coherent contributions to the pulse unitary that would traditionally be considered sources of error are treated as part of the gate definition, and compensated in software via single-qubit rotations. This approach enables rapid device-wide generation of high-fidelity two-qubit entangling gates, which are combined with standard calibrated gates to produce an expanded gate set. We show how these gates are directly usable as part of a quantum compiler, synthesizing generic two-qubit circuit blocks into minimal-duration sequences of the characterized gates interleaved with compensating single-qubit rotations. Benchmarking against circuits compiled using the default $CX$ gate alone on 127-qubit IBM hardware shows up to 7X improvement in success probability for Quantum Fourier Transform circuits up to 26 qubits, and up to 9X lower mean-square error in Trotter simulations of the one-dimensional transverse-field Ising model. Our hardware-agnostic characterization and compilation methodology makes it practical to scale up expressive gate sets on quantum computing architectures while minimizing the need for onerous fine-tuning of low-level control waveforms.
We propose and validate on real quantum computing hardware a new method for extended two-qubit gate set design, replacing iterative, fine calibration with fast characterization of a small number of gate parameters which are then tracked and corrected in circuit compilation. Coherent contributions to the pulse unitary that would traditionally be considered sources of error are treated as part of the gate definition, and compensated in software via single-qubit rotations. This approach enables rapid device-wide generation of high-fidelity two-qubit entangling gates, which are combined with standard calibrated gates to produce an expanded gate set. We show how these gates are directly usable as part of a quantum compiler, synthesizing generic two-qubit circuit blocks into minimal-duration sequences of the characterized gates interleaved with compensating single-qubit rotations. Benchmarking against circuits compiled using the default CX gate alone on 127-qubit IBM hardware shows up to 7X improvement in success probability for Quantum Fourier Transform circuits up to 26 qubits, and up to 9X lower mean-square error in Trotter simulations of the one-dimensional transverse-field Ising model. Our hardware-agnostic characterization and compilation methodology makes it practical to scale up expressive gate sets on quantum computing architectures while minimizing the need for onerous fine-tuning of low-level control waveforms.
Efforts to scale-up quantum computation have reached a point where the principal limiting factor is not the number of qubits, but the entangling gate infidelity. However, the highly detailed system characterization required to understand the underlying error sources is an arduous process and impractical with increasing chip size. Open-loop optimal control techniques allow for the improvement of gates but are limited by the models they are based on. To rectify the situation, we provide an integrated open-source tool set for control, calibration, and characterization (C3), capable of open-loop pulse optimization, model-free calibration, model fitting, and refinement. We present a methodology to combine these tools to find a quantitatively accurate system model, high-fidelity gates, and an approximate error budget, all based on a high-performance, feature-rich simulator. We illustrate our methods using simulated fixed-frequency superconducting qubits for which we learn model parameters with less than $1\mathrm{%}$ error and derive a coherence-limited cross-resonance gate that achieves $99.6\mathrm{%}$ fidelity without the need for calibration.
Abstract Quantum noise in real-world devices poses a significant challenge in achieving practical quantum advantage, since accurately compiled and executed circuits are typically deep and highly susceptible to decoherence. To facilitate the implementation of complex quantum algorithms on noisy hardware, we propose an approximate method for compiling target quantum circuits into brick-wall layouts. This new circuit design consists of two-qubit CNOT gates that can be directly implemented on real quantum computers, in conjunction with optimized one-qubit gates, to approximate the essential dynamics of the original circuit while significantly reducing its depth. Our approach is evaluated through numerical simulations of time-evolution circuits for the critical Ising model, quantum Fourier transformation, and Haar-random quantum circuits, as well as experiments on IBM quantum platforms. By accounting for compilation error and circuit noise, we demonstrate that time evolution and quantum Fourier transformation circuits achieve high compression rates, while random quantum circuits are less compressible. The degree of compression is related to the rate of entanglement accumulation in the target circuit. In particular, experiments on IBM platforms achieve a compression rate of 12.5 for N=12, significantly extending the application of current quantum devices. Furthermore, large-scale numerical simulations for system sizes up to N=30 reveal that the optimal depth dmax to achieve maximal overall fidelity is independent of system size N, suggesting the scalability of our method for large quantum devices in terms of quantum resources.
Abstract As quantum processors grow in scale and reliability, the need for efficient quantum gate decomposition of circuits to a set of specific available gates, becomes ever more critical. The decomposition of a particular algorithm into a sequence of these available gates is not unique. Thus, the fidelity of an algorithm’s implementation can be increased by choosing an optimized decomposition. This is true both for noisy intermediate-scale quantum platforms as well as for implementation of quantum error correction schemes. Here we present a compilation scheme which implements a general-circuit decomposition to a sequence of Ising-type, long-range, multi-qubit (MQ) entangling gates, that are separated by layers of single qubit rotations. We use trapped ions as an example in which MQ gates naturally arise, yet any system that has connectivity beyond nearest-neighbors may gain from our approach. We evaluate our methods using the quantum volume (QV) test over N qubits. In this context, our method replaces 3 N 2 / 2 two-qubit gates with 2 N + 1 MQ gates. Furthermore, our method minimizes the magnitude of the entanglement phases, which typically enables an improved implementation fidelity, by using weaker driving fields or faster realizations. We numerically test our compilation and show that, compared to conventional realizations with sequential two-qubit gates, our compilations improves the logarithm of QV by 20% to 25%.
We present an analysis of quantum circuit fidelity across the full compilation stack, from high-level gate optimization through pulse-level control. We connect a C++ circuit optimizer to a per-gate Lindblad master-equation fidelity model whose decoherence channels are cross-validated against qiskit-dynamics and whose absolute predictions are benchmarked against execution on real hardware. Across a campaign of 4,452 experiment runs over 371 benchmark circuits, gate cancellation provides the dominant improvement (d=1.66, 72% of circuits improved), while circuit size and pulse duration are the strongest negative predictors of process fidelity (input gates r=−0.78; pulse duration r=−0.73, R2=0.53). A formal ablation study shows that pass ordering has no significant effect on two-qubit gate reduction (Kruskal--Wallis p=0.302). Comparing against Qiskit transpilation levels, we show that two-qubit gate count, not total gate count, is the hardware-relevant metric: our optimizer attains superior two-qubit reduction on structured circuits (87.8% on QFT, 100% on QAOA) whereas Qiskit's larger total-gate reduction is dominated by single-qubit (u3) consolidation. Finally, executing eight circuits on the IQM Resonance Garnet processor (8/8 jobs completed, job identifiers released) reveals that the model is a consistent upper bound: it preserves the relative difficulty ordering of circuits but overestimates absolute fidelity by a mean of 0.49, quantifying the error budget (crosstalk, leakage, readout) outside a T1/T2/depolarizing model. We release the framework, data, and scripts as open source.
In the scaling development of quantum computers, the calibration process emerges as a critical challenge. Existing calibration methods, utilizing the same pulse waveform for two-qubit gates across the device, overlook hardware differences among physical qubits and lack efficient parallel calibration. In this paper, we enlarge the pulse candidates for two-qubit gates to three pulse waveforms, and introduce a fine-grained calibration protocol. In the calibration protocol, three policies are proposed to profile each qubit pair with its optimal pulse waveform. Afterwards, calibration subgraphs are introduced to enable parallel calibraton through identifying compatible calibration operations. The protocol is validated on real machine with up to 127 qubits. Real-machine experiments demonstrates a minimum gate error of 0.001 with a median error of 0.006 which is 1.84x reduction compared to default pulse waveform provided by IBM. On device level, a double fold increase in quantum volume as well as 2.3x reduction in error per layered gate are achieved. The proposed protocol leverages the potential current hardware and could server as an important step toward fault-tolerant quantum computing.
Quantum circuit compilation is a fundamental step in quantum computing, translating high-level quantum algorithms into sequences of gates executable on a specific quantum hardware. However, current compilation methods often employ static decompositions, neglecting the inherent noise characteristics of quantum devices, leading to suboptimal circuit designs and reduced fidelity. This work proposes a novel adaptive quantum circuit compilation strategy that dynamically adjusts circuit decompositions in real-time, based on continuous monitoring of hardware noise profiles. The core of this approach lies in integrating quantum error mitigation techniques with a feedback loop that iteratively refines the circuit design to minimize the detrimental effects of noise. We introduce a framework for evaluating the effectiveness of this adaptive compilation process, demonstrating potential improvements in circuit fidelity and execution time. This research directly addresses the critical need for real-time adaptive compilation, a cornerstone for the practical realization of fault-tolerant quantum computing. The presented methodology offers a promising path towards more efficient and robust quantum algorithms, ultimately contributing to the advancement of quantum information processing.