Quantum machine learning algorithms based on parameterized quantum circuits are promising candidates for near-term quantum advantage. Although these algorithms are compatible with the current generation of quantum processors, device noise limits their performance, for example by inducing an exponential flattening of loss landscapes. Error suppression schemes such as dynamical decoupling and Pauli twirling alleviate this issue by reducing noise at the hardware level. A recent addition to this toolbox of techniques is pulse-efficient transpilation, which reduces circuit schedule duration by exploiting hardware-native cross-resonance interaction. In this work, we investigate the impact of pulse-efficient circuits on near-term algorithms for quantum machine learning. We report results for two standard experiments: binary classification on a synthetic dataset with quantum neural networks and handwritten digit recognition with quantum kernel estimation. In both cases, we find that pulse-efficient transpilation vastly reduces average circuit durations and, as a result, significantly improves classification accuracy. We conclude by applying pulse-efficient transpilation to the Hamiltonian Variational Ansatz and show that it delays the onset of noise-induced barren plateaus.
State-of-the-art noisy digital quantum computers can only execute short-depth quantum circuits. Variational algorithms are a promising route to unlock the potential of noisy quantum computers since the depth of the corresponding circuits can be kept well below hardware-imposed limits. Typically, the variational parameters correspond to virtual
RZ gate angles, implemented by phase changes of calibrated pulses. By encoding the variational parameters directly as hardware pulse amplitudes and durations, we succeed in further shortening the pulse schedule and overall circuit duration. This decreases the impact of qubit decoherence and gate noise. As a demonstration, we apply our pulse-based variational algorithm to the calculation of the ground state of different hydrogen-based systems (
H2,H3, and
H4) using IBM cross-resonance-based hardware. We observe a reduction in schedule duration of up to $5\ifmmode\times\else\texttimes\fi{}$ compared to cnot-based Ans\"atze, while also reducing the measured energy. In particular, we observe a sizable improvement of the minimal energy configuration of
H3 compared to a cnot-based variational form. Finally, we discuss possible future developments including error-mitigation schemes and schedule optimizations, which will enable further improvements of our approach, paving the way towards the simulation of larger systems on noisy quantum devices.
We present a novel approach for implementing pulse-efficient SU(4) gates on cross resonance (CR)-based superconducting quantum devices. Our method introduces a parameterized unitary derived from the CR-Hamiltonian propagator, which accounts for static-
ZZinteractions. Leveraging the Weyl chamber's geometric structure, we successfully realize a continuous 2-qubit basis gate,
RZZ(θ), as an echo-free pulse schedule on the IBM Quantum deviceibm_kawasaki. We evaluate the average fidelity and gate time of various SU(4) gates generated using the
RZZ(θ)to confirm the advantages of our implementation.
We present an analysis of quantum circuit fidelity across the full compilation stack, from high-level gate optimization through pulse-level control. We connect a C++ circuit optimizer to a per-gate Lindblad master-equation fidelity model whose decoherence channels are cross-validated against qiskit-dynamics and whose absolute predictions are benchmarked against execution on real hardware. Across a campaign of 4,452 experiment runs over 371 benchmark circuits, gate cancellation provides the dominant improvement (
d=1.66, 72% of circuits improved), while circuit size and pulse duration are the strongest negative predictors of process fidelity (input gates
r=−0.78; pulse duration
r=−0.73,
R2=0.53). A formal ablation study shows that pass ordering has no significant effect on two-qubit gate reduction (Kruskal--Wallis
p=0.302). Comparing against Qiskit transpilation levels, we show that two-qubit gate count, not total gate count, is the hardware-relevant metric: our optimizer attains superior two-qubit reduction on structured circuits (87.8% on QFT, 100% on QAOA) whereas Qiskit's larger total-gate reduction is dominated by single-qubit (
u3) consolidation. Finally, executing eight circuits on the IQM Resonance Garnet processor (8/8 jobs completed, job identifiers released) reveals that the model is a consistent upper bound: it preserves the relative difficulty ordering of circuits but overestimates absolute fidelity by a mean of 0.49, quantifying the error budget (crosstalk, leakage, readout) outside a
T1/
T2/depolarizing model. We release the framework, data, and scripts as open source.
Running quantum programs is fraught with challenges on on today's noisy intermediate scale quantum (NISQ) devices. Many of these challenges originate from the error characteristics that stem from rapid decoherence and noise during measurement, qubit connections, crosstalk, the qubits themselves, and transformations of qubit state via gates. Not only are qubits not “created equal”, but their noise level also changes over time. IBM is said to calibrate their quantum systems once per day and reports noise levels (errors) at the time of such calibration. This information is subsequently used to map circuits to higher quality qubits and connections up to the next calibration point. This work provides evidence that there is room for improvement over this daily calibration cycle. It contributes a technique to measure noise levels (errors) related to qubits immediately before executing one or more sensitive circuits and shows that just-in-time noise measurements can benefit late physical qubit mappings. With this just-in-time recalibrated transpilation, the fidelity of results is improved over IBM's default mappings, which only uses their daily calibrations. The framework assess two major sources of noise, namely readout errors (measurement errors) and two-qubit gate/connection errors. Experiments indicate that the accuracy of circuit results improves by 3-304% on average and up to 400% with on-the-fly circuit mappings based on error measurements just prior to application execution.
Abstract Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on
RZX R ZX gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking and Process Tomography, we reduce gate errors by half. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.