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Scientific Reports

Native multi-qubit gates in transmon qubits via synchronous driving

Sagar Silva Pratapsi, Diogo Cruz, Paulo Sérgio de Brito André

Published Oct 29, 2024• 1 citation
Publisher

Abstract

Abstract Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on $$R_{ZX}$$ R ZX gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking and Process Tomography, we reduce gate errors by half. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.

DOI
10.1038/s41598-024-76396-9

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Abstract Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on RZXR_{ZX}RZX​ R ZX gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking and Process Tomography, we reduce gate errors by half. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.
Quantum computation holds the promise of solving computational problems which are believed to be classically intractable. However, in practice, quantum devices are still limited by their relatively short coherence times and imperfect circuit-hardware mapping. In this work, we present the parallelization of pre-calibrated pulses at the hardware level as an easy-to-implement strategy to optimize quantum gates. Focusing on RZXR_{ZX}RZX​ gates, we demonstrate that such parallelization leads to improved fidelity and gate time reduction, when compared to serial concatenation. As measured by Cycle Benchmarking, our most modest fidelity gain was from 98.16(7)% to 99.15(3)% for the application of two RZX(π/2)R_{ZX}(π/2)RZX​(π/2) gates with one shared qubit. We show that this strategy can be applied to other gates like the CNOT and CZ, and it may benefit tasks such as Hamiltonian simulation problems, amplitude amplification, and error-correction codes.
We show a pulse-efficient circuit transpilation framework for noisy quantum hardware. This is achieved by scaling cross-resonance pulses and exposing each pulse as a gate to remove redundant single-qubit operations with the transpiler. Crucially, no additional calibration is needed to yield better results than a CNOT-based transpilation. This pulse-efficient circuit transpilation therefore enables a better usage of the finite coherence time without requiring knowledge of pulse-level details from the user. As demonstration, we realize a continuous family of cross-resonance-based gates for SU(4) by leveraging Cartan's decomposition. We measure the benefits of a pulse-efficient circuit transpilation with process tomography and observe up to a 50% error reduction in the fidelity of ${R}_{ZZ}(\ensuremath{\theta})$ and arbitrary SU(4) gates on IBM Quantum devices. We apply this framework for quantum applications by running circuits of the quantum approximate optimization algorithm applied to MAXCUT. For an 11-qubit nonhardware native graph, our methodology reduces the overall schedule duration by up to 52% and errors by up to 38%.
Abstract Benchmarking large-scale quantum gates, typically involving multiple native two-qubit and single-qubit gates, is crucial in quantum computing. Global fidelity, encompassing information about inter-gate correlations, offers a comprehensive metric for evaluating and optimizing gate performance, unlike the fidelities of individual local native gates. In this work, utilizing the character-average benchmarking protocol implementable in a shallow circuit, we successfully benchmark gate fidelities up to 52 qubits. Notably, we achieved a fidelity of 63.09% ± 0.23% for a 44-qubit parallel CZ gate. Utilizing the global fidelity of the parallel CZ gate, we explore the correlations among local CZ gates by introducing an inter-gate correlation metric, enabling one to simultaneously quantify crosstalk error when benchmarking gate fidelity. Finally, we apply our methods in gate optimization. By leveraging global fidelity for optimization, we enhance the fidelity of a 6-qubit parallel CZ gate from 87.65% to 92.04% and decrease the gate correlation from 3.53% to 3.22%, compared to local gate fidelity-based optimization. The experimental results align well with our established composite noise model, incorporating depolarizing and Z Z-coupling noises, and provide valuable insight into further study and mitigation of correlated noise.
Continuous gate sets are a key ingredient for near-term quantum algorithms. Here, we demonstrate a hardware-efficient, continuous set of controlled arbitrary-phase ( CZ θ ) gates acting on flux-tunable transmon qubits. This implementation is robust to control pulse distortions on time scales longer than the duration of the gate, making it suitable for deep quantum circuits. Our calibration procedure makes it possible to parameterize the continuous gate set with a single control parameter, the idle time between the two rectangular halves of the net-zero control pulse. For calibration and characterization, we develop a leakage measurement based on coherent amplification, and a new cycle design for cross-entropy benchmarking. We demonstrate gate errors of 0.7 % and leakage of 4 × 10 − 4 across the entire gate set. This native gate set has the potential to reduce the depth and improve the performance of near-term quantum algorithms compared to decompositions into CZ π gates and single-qubit gates. Moreover, we expect the calibration and benchmarking methods to find further possible applications.
Increasing quantum circuit fidelity requires an efficient instruction set to minimize errors from decoherence. The choice of a two-qubit (2Q) hardware basis gate depends on a quantum modulator's native Hamiltonian interactions and applied control drives. In this paper, we propose a collaborative design approach to select the best ratio of drive parameters that determine the best basis gate for a particular modulator. This requires considering the theoretical computing power of the gate along with the practical speed limit of that gate, given the modulator drive parameters. The practical speed limit arises from the couplers' tolerance for strong driving when one or more pumps is applied, for which some combinations can result in higher overall speed limits than others. Moreover, as this 2Q basis gate is typically applied multiple times in succession, interleaved by 1Q gates applied directly to the qubits, the speed of the 1Q gates can become a limiting factor for the quantum circuit, particularly as the pulse length of the 2Q basis gate is optimized. We propose parallel-drive to drive the modulator and qubits simultaneously, allowing a richer capability of the 2Q basis gate and in some cases for this 1Q drive time to be absorbed entirely into the 2Q operation. This allows increasingly short duration 2Q gates to be more practical while mitigating a significant source of overhead in some quantum systems. On average, this approach can decrease circuit duration by 17.8% and decrease infidelity for random 2Q gates by 10.5% compared to the currently best reported basic 2Q gate, √iSWAP.
While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an 18% reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a 25% reduction from the canonical eight multi-qubit implementations for linearly connected qubits.