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arXiv:2304.09111 · Quantum Science and Technology

Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors

Nandini Muthusubramanian, Matvey I. Finkel, Pim Duivestein, Christos Zachariadis, S. L. M. van der Meer, H. M. Veen, Marc Beekman, Thijs Stavenga, Alessandro Bruno, L. DiCarlo

Published Dec 29, 2023• 21 citations
arXivHTMLPDF

Abstract

Abstract We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ∼ 100 M H z in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer center to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.

DOI
10.1088/2058-9565/ad199c

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Abstract We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ∼ 100 M H z in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer center to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (  CVA\:{CV}_{A}CVA​ ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving  CVRN\:{CV}_{{R}_{N}}CVRN​​ down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
Variability in Josephson junction area and resistance remains a central challenge in scaling fixed-frequency superconducting qubit architectures, where resistance fluctuations translate into qubit-frequency dispersion and potential frequency collisions. Here, we present a fabrication strategy that combines large-area process control on 200 mm wafers with chip-level electrical fine-tuning to improve junction-resistance repeatability. Within a central 80 × 80 mm 2 field on 200 mm wafers, the Manhattan-style aluminum junction process yielded relative standard deviations of 5.1–5.2% in junction area (RSD A ) and 5.8–7.2% in room-temperature resistance (RSD R ). Alternating-bias assisted annealing (ABAA) further reduced chip-level RSD R to 1.3% in a chip with all 20 junctions tuned and to 1.7% for 16 tuned junctions in a cryogenically characterized 20-qubit chip. In a cross-chip comparison, the coherence distributions of the ABAA-treated chip and the untreated reference chip overlapped. These results show that large-area feed-forward correction and post-fabrication tuning can improve junction-parameter repeatability in fixed-frequency superconducting circuits.
Abstract Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current I c variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ≡ σ I c / I c ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown σ I c / I c = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having σ I c / I c < 1.0% (equivalent to σ f / f < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.
Josephson junctions are the principal circuit element in numerous superconducting quantum information devices and can be readily integrated into large-scale electronics. However, device integration at the wafer scale necessarily depends on having a reliable, high-fidelity, and high-yield fabrication method for creating Josephson junctions. When creating Al/AlO x based superconducting qubits, the standard Josephson junction fabrication method relies on a sub-micron suspended resist bridge, known as a Dolan bridge, which tends to be particularly fragile and can often times fracture during the resist development process, ultimately resulting in device failure. In this work, we demonstrate a unique Josephson junction lithography mask design that incorporates stress-relief channels. Our simulation results show that the addition of stress-relief channels reduces the lateral stress in the Dolan bridge by more than 70% for all the bridge geometries investigated. In practice, our novel mask design significantly increased the survivability of the bridge during device processing, resulting in 100% yield for over 100 Josephson junctions fabricated.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.