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Scientific Reports

Multi-stage suppression of Josephson junction variability with wafer-scale uniformity in 20-qubit superconducting circuits

Hyeokshin Kwon, Dae-Yun Kim, Dae Seok Han, Kiho Kim, Hyoung Kug Kim, Geunyong Kim, June-Young M. Lee, Chungsun Lee, Jaeho Shin

Published Sep 15, 2026• 0 citations
Publisher

Abstract

Variability in Josephson junction area and resistance remains a central challenge in scaling fixed-frequency superconducting qubit architectures, where resistance fluctuations translate into qubit-frequency dispersion and potential frequency collisions. Here, we present a fabrication strategy that combines large-area process control on 200 mm wafers with chip-level electrical fine-tuning to improve junction-resistance repeatability. Within a central 80 × 80 mm 2 field on 200 mm wafers, the Manhattan-style aluminum junction process yielded relative standard deviations of 5.1–5.2% in junction area (RSD A ) and 5.8–7.2% in room-temperature resistance (RSD R ). Alternating-bias assisted annealing (ABAA) further reduced chip-level RSD R to 1.3% in a chip with all 20 junctions tuned and to 1.7% for 16 tuned junctions in a cryogenically characterized 20-qubit chip. In a cross-chip comparison, the coherence distributions of the ABAA-treated chip and the untreated reference chip overlapped. These results show that large-area feed-forward correction and post-fabrication tuning can improve junction-parameter repeatability in fixed-frequency superconducting circuits.

DOI
10.1038/s41598-026-70944-1

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Variability in Josephson junction area and resistance remains a central challenge in scaling fixed-frequency superconducting qubit architectures, where resistance fluctuations translate into qubit-frequency dispersion and potential frequency collisions. Here, we present a fabrication strategy that combines large-area process control on 200 mm wafers with chip-level electrical fine-tuning to improve junction-resistance repeatability. Within a central 80 × 80 mm 2 field on 200 mm wafers, the Manhattan-style aluminum junction process yielded relative standard deviations of 5.1–5.2% in junction area (RSD A ) and 5.8–7.2% in room-temperature resistance (RSD R ). Alternating-bias assisted annealing (ABAA) further reduced chip-level RSD R to 1.3% in a chip with all 20 junctions tuned and to 1.7% for 16 tuned junctions in a cryogenically characterized 20-qubit chip. In a cross-chip comparison, the coherence distributions of the ABAA-treated chip and the untreated reference chip overlapped. These results show that large-area feed-forward correction and post-fabrication tuning can improve junction-parameter repeatability in fixed-frequency superconducting circuits.
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Abstract Quantum bits, or qubits, are an example of coherent circuits envisioned for next-generation computers and detectors. A robust superconducting qubit with a coherent lifetime of O(100 µs) is the transmon: a Josephson junction functioning as a non-linear inductor shunted with a capacitor to form an anharmonic oscillator. In a complex device with many such transmons, precise control over each qubit frequency is often required, and thus variations of the junction area and tunnel barrier thickness must be sufficiently minimized to achieve optimal performance while avoiding spectral overlap between neighboring circuits. Simply transplanting our recipe optimized for single, stand-alone devices to wafer-scale (producing 64, 1x1 cm dies from a 150 mm wafer) initially resulted in global drifts in room-temperature tunneling resistance of ± 30%. Inferring a critical current I c variation from this resistance distribution, we present an optimized process developed from a systematic 38 wafer study that results in < 3.5% relative standard deviation (RSD) in critical current ( ≡ σ I c / I c ) for 3000 Josephson junctions (both single-junctions and asymmetric SQUIDs) across an area of 49 cm2. Looking within a 1x1 cm moving window across the substrate gives an estimate of the variation characteristic of a given qubit chip. Our best process, utilizing ultrasonically assisted development, uniform ashing, and dynamic oxidation has shown σ I c / I c = 1.8% within 1x1 cm, on average, with a few 1x1 cm areas having σ I c / I c < 1.0% (equivalent to σ f / f < 0.5%). Such stability would drastically improve the yield of multi-junction chips with strict critical current requirements.
Superconducting quantum processors are one of the leading platforms for realizing scalable fault-tolerant quantum computation (FTQC). The recent demonstration of post-fabrication tuning of Josephson junctions using alternating-bias assisted annealing (ABAA) technique and a reduction in junction loss after ABAA illuminates a promising path towards precision tuning of qubit frequency while maintaining high coherence. Here, we demonstrate precision tuning of the maximum∣0⟩→∣1⟩\vert 0\rangle\rightarrow\vert 1\rangle∣0⟩→∣1⟩transition frequency(f01max⁡)(f_{01}^{\max})(f01max​)of tunable transmon qubits by performing ABAA at room temperature using commercially available test equipment. We characterize the impact of junction relaxation and aging on resistance spread after tuning, and demonstrate a frequency equivalent tuning precision of 7.7 MHz (0.17%) based on targeted resistance tuning on hundreds of qubits, with a resistance tuning range up to 18.5%. Cryogenic measurements on tuned and untuned qubits show evidence of improved coherence after ABAA with no significant impact on tunability. Despite a small global offset, we show an empiricalf01max⁡f_{01}^{\max}f01max​tuning precision of 18.4 MHz by tuning a set of multi-qubit processors targeting their designed Hamiltonians. We experimentally characterize high-fidelity parametric resonance iSWAP gates on two ABAA-tuned 9-qubit processors with fidelity as high as 99.51±0.20%\pm 0.20{\%}±0.20%. On the best-performing device, we measured across the device a median fidelity of 99.22% and an average fidelity of 99.13$\pm$0.12%. Yield modeling analysis predicts high detuning-edge-yield using ABAA beyond the 1000-qubit scale. These results demonstrate the cutting-edge capability of frequency targeting using ABAA and open up a new avenue to systematically improving Hamiltonian targeting and optimization for scaling high-performance superconducting quantum processors.
One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (  CVA\:{CV}_{A}CVA​ ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving  CVRN\:{CV}_{{R}_{N}}CVRN​​ down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
Abstract The uniformity of Josephson-junction (JJ) characteristics is crucial in wafer-scale superconducting quantum-bit (qubit) integration. To achieve the level of accuracy demanded the circuits, every detail of the fabrication process needs to be optimized. Here we reveal that the junction-resistance (R N) variations of Al/AlO x /Al JJs are affected by the metal deposition on the sidewall of the resist mask during shadow evaporation. The effect is reproduced in numerical simulation using a simple model taking into account the resist structure and the evaporation angle. To overcome the issue, we introduce a two-step shadow evaporation method to reduce the variation of R N. As a result, the coefficient of variations across a 3-inch wafer decreases from 6.7% to 4.5%, achieving 1.1% in a chip with an area of 10 mm × 10 mm. This method is promising for developing large-scale superconducting quantum computers.
Superconducting qubits are a promising route to achieving large-scale quantum computers. A key challenge in realising large-scale superconducting quantum processors involves mitigating frequency collisions. In this paper, we present an approach to tuning fixed-frequency qubits with the use of an electron beam to locally anneal the Josephson junction. We demonstrate the ability to both increase and decrease the junction barrier resistance. The technique shows an improvement in wafer scale frequency targetting by assessing the frequency collisions in our qubit architecture. Coherence measurements are also done to evaluate the performance before and after tuning. The tuning process utilises a standard electron beam lithography system, ensuring reproducibility and implementation by any group capable of fabricating these Josephson junctions. This technique has the potential to significantly improve the performance of large-scale quantum computing systems, thereby paving the way for the future of quantum computing.