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Japanese Journal of Applied Physics

Uniformity improvement of Josephson-junction resistance by considering sidewall deposition during shadow evaporation for large-scale integration of qubits

Tsuyoshi Takahashi, Norinao Kouma, Yoshiyasu Doi, Shintaro Sato, Shuhei Tamate, Yasunobu Nakamura

Published Nov 14, 2022• 12 citations
Publisher

Abstract

Abstract The uniformity of Josephson-junction (JJ) characteristics is crucial in wafer-scale superconducting quantum-bit (qubit) integration. To achieve the level of accuracy demanded the circuits, every detail of the fabrication process needs to be optimized. Here we reveal that the junction-resistance (R N) variations of Al/AlO x /Al JJs are affected by the metal deposition on the sidewall of the resist mask during shadow evaporation. The effect is reproduced in numerical simulation using a simple model taking into account the resist structure and the evaporation angle. To overcome the issue, we introduce a two-step shadow evaporation method to reduce the variation of R N. As a result, the coefficient of variations across a 3-inch wafer decreases from 6.7% to 4.5%, achieving 1.1% in a chip with an area of 10 mm × 10 mm. This method is promising for developing large-scale superconducting quantum computers.

DOI
10.35848/1347-4065/aca256

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quant-pharXiv:2605.30768•Jun 1, 2026•0 citations
Abstract The uniformity of Josephson-junction (JJ) characteristics is crucial in wafer-scale superconducting quantum-bit (qubit) integration. To achieve the level of accuracy demanded the circuits, every detail of the fabrication process needs to be optimized. Here we reveal that the junction-resistance (R N) variations of Al/AlO x /Al JJs are affected by the metal deposition on the sidewall of the resist mask during shadow evaporation. The effect is reproduced in numerical simulation using a simple model taking into account the resist structure and the evaporation angle. To overcome the issue, we introduce a two-step shadow evaporation method to reduce the variation of R N. As a result, the coefficient of variations across a 3-inch wafer decreases from 6.7% to 4.5%, achieving 1.1% in a chip with an area of 10 mm × 10 mm. This method is promising for developing large-scale superconducting quantum computers.
One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (  CVA\:{CV}_{A}CVA​ ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving  CVRN\:{CV}_{{R}_{N}}CVRN​​ down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
Abstract The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where Josephson junction critical current reproducibility over a chip is crucial. Here, we report on a robust chip scale Al/AlO x /Al junctions fabrication method due to comprehensive study of shadow evaporation and oxidation steps. We experimentally demonstrate the evidence of optimal Josephson junction electrodes thickness, deposition rate and deposition angle, which ensure minimal electrode surface and line edge roughness. The influence of oxidation method, pressure and time on critical current reproducibility is determined. With the proposed method we demonstrate Al/AlO x /Al junction fabrication with the critical current variation (σ/⟨Ic⟩)(\sigma /\langle {I_{c} } \rangle )(σ/⟨Ic​⟩) ( σ / ⟨ I c ⟩ ) less than 3.9% (from 150 × 200 to 150 × 600 nm 2 area) and 7.7% (for 100 × 100 nm 2 area) over 20 × 20 mm 2 chip. Finally, we fabricate separately three 5 × 10 mm 2 chips with 18 transmon qubits (near 4.3 GHz frequency) showing less than 1.9% frequency variation between qubits on different chips. The proposed approach and optimization criteria can be utilized for a robust wafer-scale superconducting qubit circuits fabrication.
The most commonly used physical realization of superconducting qubits for quantum circuits is a transmon. There are a number of superconducting quantum circuits applications, where Josephson junction critical current reproducibility over a chip is crucial. Here, we report on a robust chip scale Al/AlOx/AlAl/AlO_x/AlAl/AlOx​/Al junctions fabrication method due to comprehensive study of shadow evaporation and oxidation steps. We experimentally demonstrate the evidence of optimal Josephson junction electrodes thickness, deposition rate and deposition angle, which ensure minimal electrode surface and line edge roughness. The influence of oxidation method, pressure and time on critical current reproducibility is determined. With the proposed method we demonstrate Al/AlOx/AlAl/AlO_x/AlAl/AlOx​/Al junction fabrication with the critical current variation (σ/Icσ/I_cσ/Ic​) less than 3.9% (from 150×200150\times200150×200 to 150×600150\times600150×600 nm2nm^2nm2 area) and 7.7% (for 100×100100\times100100×100 nm2nm^2nm2 area) over 20×2020\times2020×20 mm2mm^2mm2 chip. Finally, we fabricate separately three 5×105\times105×10 mm2mm^2mm2 chips with 18 transmon qubits (near 4.3 GHz frequency) showing less than 1.9% frequency variation between qubit on different chips. The proposed approach and optimization criteria can be utilized for a robust wafer-scale superconducting qubit circuits fabrication.
We introduce a simplified fabrication technique for Josephson junctions and demonstrate superconducting Xmon qubits with T1 relaxation times averaging above 50 μs (Q>1.5×106). Current shadow-evaporation techniques for aluminum-based Josephson junctions require a separate lithography step to deposit a patch that makes a galvanic, superconducting connection between the junction electrodes and the circuit wiring layer. The patch connection eliminates parasitic junctions, which otherwise contribute significantly to dielectric loss. In our patch-integrated cross-type junction technique, we use one lithography step and one vacuum cycle to evaporate both the junction electrodes and the patch. This eliminates a key bottleneck in manufacturing superconducting qubits by reducing the fabrication time and cost. In a study of more than 3600 junctions, we show an average resistance variation of 3.7% on a wafer that contains forty 0.5×0.5-cm2 chips, with junction areas ranging between 0.01 and 0.16 μm2. The average on-chip spread in resistance is 2.7%, with 20 chips varying between 1.4% and 2%. For the junction sizes used for transmon qubits, we deduce a wafer-level transition-frequency variation of 1.7%–2.5%. We show that 60%–70% of this variation is attributed to junction-area fluctuations, while the rest is caused by tunnel-junction inhomogeneity. Such high frequency predictability is a requirement for scaling-up the number of qubits in a quantum computer.
Variability in Josephson junction area and resistance remains a central challenge in scaling fixed-frequency superconducting qubit architectures, where resistance fluctuations translate into qubit-frequency dispersion and potential frequency collisions. Here, we present a fabrication strategy that combines large-area process control on 200 mm wafers with chip-level electrical fine-tuning to improve junction-resistance repeatability. Within a central 80 × 80 mm 2 field on 200 mm wafers, the Manhattan-style aluminum junction process yielded relative standard deviations of 5.1–5.2% in junction area (RSD A ) and 5.8–7.2% in room-temperature resistance (RSD R ). Alternating-bias assisted annealing (ABAA) further reduced chip-level RSD R to 1.3% in a chip with all 20 junctions tuned and to 1.7% for 16 tuned junctions in a cryogenically characterized 20-qubit chip. In a cross-chip comparison, the coherence distributions of the ABAA-treated chip and the untreated reference chip overlapped. These results show that large-area feed-forward correction and post-fabrication tuning can improve junction-parameter repeatability in fixed-frequency superconducting circuits.
Geometric dependence of critical-current variation in Al/AlOx{\rm _x}x​/Al Josephson junctions: a model-based analysis
Achieving uniform critical current across Josephson junctions is essential for the large-scale integration of superconducting quantum circuits. In this work, we statistically analyzed the variation of the critical current of Al/AlOx{\rm _x}x​/Al junctions using room-temperature tunnel resistance statistics, and identified the dominant contribution among the modeled sources of the variation based on their dependence on geometry and deposition conditions of junctions. Our model-based analysis reveals that fluctuations in the Al film thickness play the dominant role among the modeled contributing factors. Based on this analysis, we found that, in Dolan-bridge double-angle deposition, adopting a deposition angle of 30-degree for bilayer junctions significantly improves uniformity, yielding a relative standard deviation of 1.2% (0.5%) across a 9.75 mm (1.5 mm) square region.