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arXiv:2502.00255 · Superconductivity

Stress accommodation in nanoscale dolan bridges designed for superconducting qubits

Sueli Skinner Ramos, Matthew Freeman, Douglas V. Pete, Rupert Lewis, Matt Eichenfield, Charles Thomas Harris

Published Mar 18, 2025• 2 citations
arXivHTMLPDF

Abstract

Josephson junctions are the principal circuit element in numerous superconducting quantum information devices and can be readily integrated into large-scale electronics. However, device integration at the wafer scale necessarily depends on having a reliable, high-fidelity, and high-yield fabrication method for creating Josephson junctions. When creating Al/AlO x based superconducting qubits, the standard Josephson junction fabrication method relies on a sub-micron suspended resist bridge, known as a Dolan bridge, which tends to be particularly fragile and can often times fracture during the resist development process, ultimately resulting in device failure. In this work, we demonstrate a unique Josephson junction lithography mask design that incorporates stress-relief channels. Our simulation results show that the addition of stress-relief channels reduces the lateral stress in the Dolan bridge by more than 70% for all the bridge geometries investigated. In practice, our novel mask design significantly increased the survivability of the bridge during device processing, resulting in 100% yield for over 100 Josephson junctions fabricated.

DOI
10.1016/j.supcon.2025.100158

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Josephson junctions are the principal circuit element in numerous superconducting quantum information devices and can be readily integrated into large-scale electronics. However, device integration at the wafer scale necessarily depends on having a reliable, high-fidelity, and high-yield fabrication method for creating Josephson junctions. When creating Al/AlO x based superconducting qubits, the standard Josephson junction fabrication method relies on a sub-micron suspended resist bridge, known as a Dolan bridge, which tends to be particularly fragile and can often times fracture during the resist development process, ultimately resulting in device failure. In this work, we demonstrate a unique Josephson junction lithography mask design that incorporates stress-relief channels. Our simulation results show that the addition of stress-relief channels reduces the lateral stress in the Dolan bridge by more than 70% for all the bridge geometries investigated. In practice, our novel mask design significantly increased the survivability of the bridge during device processing, resulting in 100% yield for over 100 Josephson junctions fabricated.
One of the practical limitations of solid-state superconducting quantum processors is the collision of the qubit resonance frequencies, caused by their deviation from the design specifications due to the low reproducibility in qubit fabrication. Josephson junction 100 nm-scale nonlinear inductance of the qubits still suffers from Dolan-bridge shadow evaporation process. Here, we report on a robust wafer-scale Al/AlOx/Al Dolan-bridge Josephson junction (JJ) process using preliminary shadow evaporation bias resist mask correction and comprehensive oxidation optimization. We introduce a topology correction model for two-layer resist mask biasing at a wafer-scale, which takes into account an evaporation source geometry. It results in Josephson junction area variation coefficient (  CVA\:{CV}_{A}CVA​ ) improvement down to 1.1% for the critical dimensions from 130 × 170 nm2 to 130 × 670 nm2 over 70 × 70 mm2 (49 cm2) wafer working area. Next, we investigate JJ oxidation process (oxidation method, pressure and time) and its impact on the room temperature resistance reproducibility. Finally, we combine both shadow evaporation bias correction and oxidation best practices for 4-inch wafers, improving  CVRN\:{CV}_{{R}_{N}}CVRN​​ down to 6.0/5.2/4.1% for 0.025 µm2 JJ area and 4.0/3.4/2.3% for 0.090 µm2 JJ area for 49/25/16 cm2 wafer working area correspondingly. The proposed model and oxidation method can be useful for robust wafer-scale superconducting quantum processors fabrication.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g. in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical currentICof the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used forICand process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
The present thesis focuses on the laboratory fabrication of Al/AlOₓ/Al Josephson junctions using a bridge-free shadow evaporation technique, developed within the broader context of superconducting technologies for quantum computing. The interest in such devices arises from the central role played by the Josephson junction in superconducting qubits: unlike a purely harmonic LC oscillator, characterized by equally spaced energy levels, the presence of the junction introduces a nonlinearity that leads to an anharmonic energy spectrum. This allows for the selective addressing of the fundamental transition, which is a necessary condition for implementing a circuit-based qubit. In this framework, the quality of the AlOₓ tunnel barrier and of the metal interfaces is of crucial importance, as it directly affects not only the static electrical parameters of the junction but also dielectric losses and, more generally, the performance of the device in quantum applications. Following a theoretical overview of superconducting qubits and the physics of Al/AlOₓ/Al Josephson junctions, the work focuses on the experimental implementation and optimization of a bridge-free fabrication approach, adopted as an alternative to conventional suspended-bridge techniques. This method preserves the advantages of in-situ shadow evaporation for barrier formation while replacing the mechanical fragility of the suspended bridge with a geometrical control of the resist undercut. The operating principle relies on engineering an asymmetric profile in a bilayer resist system such that, during the two angled evaporations, only one deposition reaches the substrate along the connection lines, while the other is deposited on the resist sidewalls and subsequently removed during lift-off. In the central region, the overlap of the two evaporated aluminum layers, separated by an intermediate oxidation step, defines the Al/AlOₓ/Al superconductor–insulator–superconductor structure. This approach results in a more robust masking scheme compared to suspended-bridge processes, albeit at the cost of increased sensitivity to the precise definition and reproducibility of the undercut. The experimental activity was structured in several stages. First, the positive resists PMMA and MMA, used to form the bilayer lithographic stack, were characterized in order to determine their response as a function of electron-beam exposure dose and development conditions. A calibration mask consisting of an array of square patterns exposed at varying doses was employed to extract contrast curves and identify suitable exposure parameters. The development depth was quantitatively measured using atomic force microscopy (AFM), enabling a direct correlation between exposure dose and resulting resist profile. This step proved essential for selecting the most appropriate resist configuration capable of producing a controlled undercut compatible with the requirements of the bridge-free process. Subsequently, the lithographic process and evaporation geometry were calibrated through iterative refinement of the mask design, exposure parameters, and development conditions. Cross-sectional analysis, obtained via controlled sample cleaving followed by scanning electron microscopy (SEM), played a key role in assessing the three-dimensional profile of the resist, verifying the presence and quality of the undercut, and identifying potential structural instabilities such as resist collapse. At the same time, modifications were introduced to the evaporation system to enable deposition at the desired angles. This required the design of a new sample holder and a complete recalibration of the quartz crystal microbalance, as the altered geometry significantly affected the relationship between the nominal thickness reading and the actual film thickness deposited on the sample. A further important aspect of the work involved the progressive design and optimization of the full device mask, including contact pads, alignment markers, and the active junction region. The evolution of the layout, from initial test structures to the final configuration, was guided by experimental observations of pattern distortions and dose non-uniformities. It was found that the writing order of the electron-beam lithography pattern generator could significantly influence the final pattern quality, introducing systematic variations in feature definition. To mitigate this effect, a constrained writing sequence was implemented, ensuring improved reproducibility of the exposure process. Once all process parameters were stabilized, a comprehensive Standard Operating Procedure (SOP) was established, covering both the fabrication of Cr/Au contact structures and the subsequent lithography, angled evaporation, oxidation, and lift-off steps required for the realization of the Josephson junction. Finally, prior to fabricating fully oxidized junctions, a preliminary electrical validation of the process was carried out by producing test structures without the intermediate oxidation step. This allowed for the verification of electrical continuity in the aluminum structures. Measurements performed using a probe station confirmed ohmic behavior and the absence of macroscopic discontinuities in the conduction path. The measured resistance values were higher than those predicted using bulk aluminum resistivity; however, this discrepancy is consistent with the well-known behavior of thin evaporated films, in which surface scattering, grain boundaries, and interface effects lead to an increased effective resistivity. Although these measurements do not yet constitute a full characterization of the Josephson junction in the quantum regime, they provide an essential validation of the fabrication process and the structural integrity of the devices. In conclusion, this work enabled the development and calibration of a bridge-free fabrication process for Al/AlOₓ/Al Josephson junctions, highlighting the strong interplay between lithographic control, evaporation geometry, barrier formation, and electrical response. The main contribution of the thesis lies in transforming a conceptual fabrication approach into a structured and reproducible experimental procedure, based on resist characterization, cross-sectional analysis, instrumental recalibration, and preliminary electrical validation. The results obtained provide a solid foundation for further optimization of the tunnel barrier, cryogenic characterization, and integration of these junctions into superconducting circuits for quantum computing applications.
Airbridges are essential for creating high-performance, low-parasitic interconnects in integrated circuits and quantum devices. Conventional multi-step fabrication methods hinder miniaturization and introduce process-related defects. We report a simplified process for fabricating nanoscale airbridges using only a single electron-beam lithography step. By optimizing a multilayer resist stack with a triple-exposure-dose scheme and a thermal reflow step, we achieve smooth, suspended metallic bridges with sub-200-nm features that exhibit robust mechanical stability. Fabricated within a gradiometric SQUID design for superconducting transmon qubits, these airbridges introduce no measurable additional loss in the relaxation time T1T_1T1​, while enabling a 2.5-fold enhancement of the dephasing time T2∗T_2^*T2∗​. This efficient method offers a practical route toward integrating high-performance three-dimensional interconnects in advanced quantum and nano-electronic devices.
The authors have developed two distinct processes for the fabrication of mesoscopic Josephson junction qubits that are compatible with conventional CMOS processing. These devices, based on superconducting Al/Al2O3/Al tunnel junctions, are fabricated by electron beam lithography using single-layer and multi-layer resists. The new single-layer resist process is found to have significant advantages over conventional fabrication methods using suspended tri-layer shadow masks. It is simpler and more accurate to implement, and avoids the significant areas of redundant metallisation that are an unavoidable by-product of the tri-layer shadow mask method.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-μ m sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross -type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross -type aluminum JJs.