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arXiv:1105.4909

Monolithic Microfabricated Symmetric Ion Trap for Quantum Information Processing

Fayaz A. Shaikh, Arkadaş Özakın, Jason Amini, Harley Hayden, C. S. Pai, Curtis Volin, Douglas R. Denison, Daniel L. Faircloth, Alexa W. Harter, Richart E. Slusher

Published May 24, 2011• 1 citation
arXivHTMLPDF

Abstract

We describe a novel monolithic ion trap that combines the flexibility and scalability of silicon microfabrication technologies with the superior trapping characteristics of traditional four-rod Paul traps. The performace of the proposed microfabricated trap approaches that of the macroscopic structures. The fabrication process creates an angled through-chip slot which allows backside ion loading and through-laser access while avoiding surface light scattering and dielectric charging. The trap geometry and dimensions are optimized for confining long ion chains with equal ion spacing [G.-D. Lin, et al., Europhys. Lett. 86, 60004 (2009)]. Control potentials have been derived to produce linear, equally spaced ion chains of up to 50 ions spaced at 10 um. With the deep trapping depths achievable in this design, we expect that these chains will be sufficiently long-lived to be used in quantum simulations of magnetic systems [E.E. Edwards, et al., Phys. Rev. B 82, 060412(R) (2010)]. The trap is currently being fabricated at Georgia Tech using VLSI techniques.

DOI
10.48550/arxiv.1105.4909

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A design is proposed for a novel ion trap quantum processor chip, microfabricated using a process based on planar silica-on-silicon techniques. The trap electrodes are of gold-coated silica and are spaced by highly doped silicon in a monolithic structure. This design allows a unit aspect-ratio trap with an ion-electrode separation below 100 μm, when using current fabrication techniques. The trapping potential is modelled and the operating parameters required to achieve motional frequencies of a few MHz are calculated. RF loss and the resultant heating of the trap chip are not found to be a factor limiting the trap's operation. This monolithic unit aspect-ratio trap is therefore expected to exhibit a deep potential well, high trap efficiency, and a low RF loss, when compared to other microfabricated traps. This technological approach is in principle scaleable to complex devices, and may form the basis for large-scale ion trap quantum processors.
Trapped ions within Paul traps have shown to be a promising architecture in the realisation of a quantum information processor together with the ability of providing quantum simulations. Linear Paul traps have demonstrated long coherence times with ions being well isolated from the environment, single and multi-qubit gates and the high fidelity detection of states. The scalability to large number of qubits, incorporating all the previous achievements requires an array of linear ion traps. Microfabrication techniques allow for fabrication and micron level accuracy of the trap electrode dimensions through photolithography techniques. The first part of this thesis presents the experiential setup and trapping of Yb+ ions needed to test large ion trap arrays. This include vacuum systems that can host advanced symmetric and asymmetric ion traps with up to 90 static voltage control electrodes. Demonstration of a single trapped Yb+ ion within a two-layer macroscopic ion trap is presented. with an ion-electrode distance of 310(10) µm. The anomalous heating rate and spectral noise density of the trap was measured, a main form of decoherence within ion traps. The second half of this thesis presents the design and fabrication of multi-layer asymmetric ion traps. This allows for isolated electrodes that cannot be accessed via surface pathways, allowing for higher density of electrodes as well as creating novel trap designs that allow for the potential of quantum simulations to be demonstrated. These include two-dimensional lattices and ring trap designs in which the isolated electrodes provide more control in the ion position. For the microfabrication of these traps I present a novel high-aspect ratio electroplated electrode design that provides shielding of the dielectric layer. This provides a means to mitigate stray electric field due to charge build up on the dielectric surfaces. Electrical testing of the trap structures was performed to test bulk breakdown and surface flashover of the ion trap architectures. Results showed sufficient isolation between electrodes for both radio frequency and static breakdown. Surface flashover voltage measurements over the dielectric layer showed an improvement of more than double over previous results using a new fabrication technique. This will allow for more powerful ion trap chips needed for the next generation of microfabricated ion trap arrays for scalable quantum technologies.
This paper describes a microfabricated linear segmented RF Paul trap for atomic quantum technologies. The microtrap geometry, initially demonstrated in [1], has been augmented and includes a linear array of trapping segments. Trapping of individual and strings of 88Sr+ ions is demonstrated. The fabrication process has been optimized such that for 80 % of the fabricated devices, the achieved geometry is within ± 5 μm (or ± 3 %) of a prescribed design. This is critical for scalable quantum information processing, where arrays of traps with consistent parameters are required.
The prospect of building a quantum information processor underlies many recent advances ion trap fabrication techniques. Potentially, a quantum computer could be constructed from a large array of interconnected ion traps. We report on a micrometer-scale ion trap, fabricated from bulk silicon using micro-electromechanical systems (MEMS) techniques. The trap geometry is relatively simple in that the electrodes lie in a single plane beneath the ions. In such a trap we confine laser-cooled 24Mg+ ions approximately 40 microns above the surface. The fabrication technique and planar electrode geometry together make this approach amenable to scaling up to large trap arrays. In addition we observe that little laser cooling light is scattered by the electrodes.
Abstract Scaling trapped-ion quantum computing will require robust trapping of at least hundreds of ions over long periods, while increasing the complexity and functionality of the trap itself. Symmetric three-dimensional (3D) structures enable high trap depth, but microfabrication techniques are generally better suited to planar structures that produce less ideal conditions for trapping. We present an ion trap fabricated on stacked eight-inch wafers in a large-scale micro-electro-mechanical system microfabrication process that provides reproducible traps at a large volume. Electrodes are patterned on the surfaces of two opposing wafers bonded to a spacer, forming a 3D structure with 2.5 μm standard deviation in alignment across the stack. We implement a design achieving a trap depth of 1 eV for a 40Ca+ ion held at 200 μm from either electrode plane. We characterize traps, achieving measurement agreement with simulations to within ±5% for mode frequencies spanning 0.6–3.8 MHz, and evaluate stray electric field across multiple trapping sites. We measure motional heating rates over an extensive range of trap frequencies, and temperatures, observing 40 phonons/s at 1 MHz and 185 K. This fabrication method provides a highly scalable approach for producing a new generation of 3D ion traps.