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International Conference on Solid-State Sensors, Actuators and Microsystems

Silicon microfabricated linear segmented ion traps for quantum technologies

Kaushal Choonee, G. Wilpers, Alastair G. Sinclair

Published Jun 1, 2017• 2 citations
Publisher

Abstract

This paper describes a microfabricated linear segmented RF Paul trap for atomic quantum technologies. The microtrap geometry, initially demonstrated in [1], has been augmented and includes a linear array of trapping segments. Trapping of individual and strings of 88Sr+ ions is demonstrated. The fabrication process has been optimized such that for 80 % of the fabricated devices, the achieved geometry is within ± 5 μm (or ± 3 %) of a prescribed design. This is critical for scalable quantum information processing, where arrays of traps with consistent parameters are required.

DOI
10.1109/transducers.2017.7994124

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This paper describes a microfabricated linear segmented RF Paul trap for atomic quantum technologies. The microtrap geometry, initially demonstrated in [1], has been augmented and includes a linear array of trapping segments. Trapping of individual and strings of 88Sr+ ions is demonstrated. The fabrication process has been optimized such that for 80 % of the fabricated devices, the achieved geometry is within ± 5 μm (or ± 3 %) of a prescribed design. This is critical for scalable quantum information processing, where arrays of traps with consistent parameters are required.
Segmented linear ion trap arrays are versatile devices that are increasingly used to study quantum physics and demonstrate the fundamental principles of quantum information processing. Traps with three-dimensional (3-D) electrode geometries can create a superior confining potential for ions. However, the realization of a monolithic 3-D microchip trap with scalable fabrication technology remains challenging. In this paper the microfabrication of a monolithic array of 3-D ion microtraps in a semiconductor chip is presented. The electrode structure is formed by micromachining a silica-on-silicon wafer and metallizing the dielectric with gold. The fabrication method uses conventional semiconductor wafer processing tools and techniques. The specific operating characteristics which demonstrate the suitability of the chosen material system and fabrication process are presented.
We describe a novel monolithic ion trap that combines the flexibility and scalability of silicon microfabrication technologies with the superior trapping characteristics of traditional four-rod Paul traps. The performace of the proposed microfabricated trap approaches that of the macroscopic structures. The fabrication process creates an angled through-chip slot which allows backside ion loading and through-laser access while avoiding surface light scattering and dielectric charging. The trap geometry and dimensions are optimized for confining long ion chains with equal ion spacing [G.-D. Lin, et al., Europhys. Lett. 86, 60004 (2009)]. Control potentials have been derived to produce linear, equally spaced ion chains of up to 50 ions spaced at 10 um. With the deep trapping depths achievable in this design, we expect that these chains will be sufficiently long-lived to be used in quantum simulations of magnetic systems [E.E. Edwards, et al., Phys. Rev. B 82, 060412(R) (2010)]. The trap is currently being fabricated at Georgia Tech using VLSI techniques.
Trapped ions within Paul traps have shown to be a promising architecture in the realisation of a quantum information processor together with the ability of providing quantum simulations. Linear Paul traps have demonstrated long coherence times with ions being well isolated from the environment, single and multi-qubit gates and the high fidelity detection of states. The scalability to large number of qubits, incorporating all the previous achievements requires an array of linear ion traps. Microfabrication techniques allow for fabrication and micron level accuracy of the trap electrode dimensions through photolithography techniques. The first part of this thesis presents the experiential setup and trapping of Yb+ ions needed to test large ion trap arrays. This include vacuum systems that can host advanced symmetric and asymmetric ion traps with up to 90 static voltage control electrodes. Demonstration of a single trapped Yb+ ion within a two-layer macroscopic ion trap is presented. with an ion-electrode distance of 310(10) µm. The anomalous heating rate and spectral noise density of the trap was measured, a main form of decoherence within ion traps. The second half of this thesis presents the design and fabrication of multi-layer asymmetric ion traps. This allows for isolated electrodes that cannot be accessed via surface pathways, allowing for higher density of electrodes as well as creating novel trap designs that allow for the potential of quantum simulations to be demonstrated. These include two-dimensional lattices and ring trap designs in which the isolated electrodes provide more control in the ion position. For the microfabrication of these traps I present a novel high-aspect ratio electroplated electrode design that provides shielding of the dielectric layer. This provides a means to mitigate stray electric field due to charge build up on the dielectric surfaces. Electrical testing of the trap structures was performed to test bulk breakdown and surface flashover of the ion trap architectures. Results showed sufficient isolation between electrodes for both radio frequency and static breakdown. Surface flashover voltage measurements over the dielectric layer showed an improvement of more than double over previous results using a new fabrication technique. This will allow for more powerful ion trap chips needed for the next generation of microfabricated ion trap arrays for scalable quantum technologies.
A design is proposed for a novel ion trap quantum processor chip, microfabricated using a process based on planar silica-on-silicon techniques. The trap electrodes are of gold-coated silica and are spaced by highly doped silicon in a monolithic structure. This design allows a unit aspect-ratio trap with an ion-electrode separation below 100 μm, when using current fabrication techniques. The trapping potential is modelled and the operating parameters required to achieve motional frequencies of a few MHz are calculated. RF loss and the resultant heating of the trap chip are not found to be a factor limiting the trap's operation. This monolithic unit aspect-ratio trap is therefore expected to exhibit a deep potential well, high trap efficiency, and a low RF loss, when compared to other microfabricated traps. This technological approach is in principle scaleable to complex devices, and may form the basis for large-scale ion trap quantum processors.
Miniaturized ion trap arrays with many trap segments present a promising architecture for scalable quantum information processing. The miniaturization of segmented linear Paul traps allows partitioning the microtrap into different storage and processing zones. The individual position control of many ions—each of them carrying qubit information in its long-lived electronic levels—by the external trap control voltages is important for the implementation of next generation large-scale quantum algorithms. We present a novel scalable microchip multi-segmented ion trap with two different adjacent zones, one for the storage and another dedicated to the processing of quantum information using single ions and linear ion crystals. A pair of radio-frequency-driven electrodes and 62 independently controlled dc electrodes allows shuttling of single ions or linear ion crystals with numerically designed axial potentials at axial and radial trap frequencies of a few megahertz. We characterize and optimize the microtrap using sideband spectroscopy on the narrow S 1/2 ↔D 5/2 qubit transition of the 40 Ca + ion, and demonstrate coherent single-qubit Rabi rotations and optical cooling methods. We determine the heating rate using sideband cooling measurements to the vibrational ground state, which is necessary for subsequent two-qubit quantum logic operations. The applicability for scalable quantum information processing is proved.
We investigate a planar ion chip design with a two-dimensional array of linear ion traps for scalable quantum information processing. Qubits are formed from the internal electronic states of trapped 40 Ca + ions. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate separately, a combination of appropriate rf and DC potentials is applied to them for stable ion confinement. Every two adjacent electrodes can generate a linear ion trap in and between the electrodes above the chip at a distance dependent on the geometrical scale and other considerations. The potential distributions are calculated by using a static electric field qualitatively. This architecture provides a conceptually simple avenue to achieving the microfabrication and large-scale quantum computation based on the arrays of trapped ions.