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Scalable Operating Strategies for Spin-Based Quantum Processors in Silicon

Cameron Jones

Published Oct 25, 2026• 0 citations
Publisher

Abstract

Silicon-based spin qubits have emerged as a promising platform for scalable quantum computation due to their compatibility with advanced semiconductor fabrication and integration with classical CMOS electronics. As fabrication capabilities advance toward larger, higher-yield devices, the field is transitioning from academic prototypes toward processors ultimately requiring millions of qubits. This shift places increasing emphasis on developing operating techniques that scale with qubit number. In this thesis, a four qubit SiMOS processor is used to investigate three key aspects of multi-qubit operation for spin-based quantum computing. First, tuning and operation techniques for parallel double-quantum-dot unit cells are developed. Electron loading strategies enable four-qubit operation in an isolated charge configuration, and universal single- and two-qubit control is demonstrated. The native gate set is characterised using gate set tomography. The processor is operated as two unit cells that can be initialised and read out in parallel, providing two independent parity measurements per shot, without increasing operation time or degrading state preparation and measurement fidelity. Second, control techniques for generating multi-qubit entangled states and executing general quantum circuits are established. Three-qubit maximally entangled states, including cluster and Greenberger–Horne–Zeilinger states, are generated and measured with a maximum fidelity of 82.5%. A Mermin value of 3.14 is achieved, certifying genuine tripartite entanglement. A fully symmetric dynamically decoupled gate sequence is developed, extending the entanglement lifetime beyond T2* to a limit set by T2-Hahn. A workflow for compiling, executing, and analysing arbitrary circuits from OpenQASM is also demonstrated. Finally, the first mid-circuit measurements in a silicon spin-qubit system are presented. This capability is extended to feedforward control, including a novel “in-layer” method that performs conditional phase operations without routing information to the classical control layer. This approach leverages measurement-induced backaction as a control mechanism. Both in-layer and FPGA-enabled feedforward strategies are benchmarked, and their dominant error channels are identified.

DOI
10.26190/unsworks/32813

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Silicon-based spin qubits have emerged as a promising platform for scalable quantum computation due to their compatibility with advanced semiconductor fabrication and integration with classical CMOS electronics. As fabrication capabilities advance toward larger, higher-yield devices, the field is transitioning from academic prototypes toward processors ultimately requiring millions of qubits. This shift places increasing emphasis on developing operating techniques that scale with qubit number. In this thesis, a four qubit SiMOS processor is used to investigate three key aspects of multi-qubit operation for spin-based quantum computing. First, tuning and operation techniques for parallel double-quantum-dot unit cells are developed. Electron loading strategies enable four-qubit operation in an isolated charge configuration, and universal single- and two-qubit control is demonstrated. The native gate set is characterised using gate set tomography. The processor is operated as two unit cells that can be initialised and read out in parallel, providing two independent parity measurements per shot, without increasing operation time or degrading state preparation and measurement fidelity. Second, control techniques for generating multi-qubit entangled states and executing general quantum circuits are established. Three-qubit maximally entangled states, including cluster and Greenberger–Horne–Zeilinger states, are generated and measured with a maximum fidelity of 82.5%. A Mermin value of 3.14 is achieved, certifying genuine tripartite entanglement. A fully symmetric dynamically decoupled gate sequence is developed, extending the entanglement lifetime beyond T2* to a limit set by T2-Hahn. A workflow for compiling, executing, and analysing arbitrary circuits from OpenQASM is also demonstrated. Finally, the first mid-circuit measurements in a silicon spin-qubit system are presented. This capability is extended to feedforward control, including a novel “in-layer” method that performs conditional phase operations without routing information to the classical control layer. This approach leverages measurement-induced backaction as a control mechanism. Both in-layer and FPGA-enabled feedforward strategies are benchmarked, and their dominant error channels are identified.
Spin qubits in silicon-MOS (SiMOS) quantum dots have recently demonstrated compatibility with existing industry standard CMOS fabrication techniques. These devices have routinely achieved single- and two-qubit gate fidelities above 99% and demonstrated highly entangled two-qubit Bell states in isolated double quantum dot (DQD) unit cells, however coupling between unit cells has remained challenging. In this work, we present a two unit cell, four-qubit SiMOS processor with universal controllability and fully parallelised state initialisation and readout. We use this processor to generate maximally entangled three-qubit states, including the Greenberger-Horne-Zeilinger (GHZ) state, and certify multipartite entanglement through violation of the classical Mermin-witness bound. By using a fully symmetric dynamically decoupled gate sequence to create our entangled states, we are able to preserve the lifetime of the entanglement beyond T2∗T_2^*T2∗​, to a time limited instead by T2HahnT_2^\textrm{Hahn}T2Hahn​. These demonstrations pave a road to the scalable operation of larger SiMOS processors, and achieving high purity, long-lived multi-qubit entangled states in them.
Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300~mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times T2∗T_2^*T2∗​ up to 41(2) μ~μ μs and Hahn-echo coherence times T2HahnT_2^{\mathrm{Hahn}}T2Hahn​ up to 1.31(4) ~ ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.
Practical quantum computers need to continuously exchange data between classical and quantum subsystems during a computation. Mid-circuit measurements of a qubits state are transferred to the classical electronics layer, and their outcome can inform feedforward operations that close the loop back to the quantum layer. These operations are crucial for fault-tolerant quantum computers, but the quantum-classical loop must be completed before the qubits decohere, presenting a substantial engineering challenge for full-scale systems comprising millions of qubits. Here we perform the first mid-circuit measurements in a system of silicon spin qubits, and show that feedforward operations can be performed without needing to route information to the classical layer. This in-layer approach leverages a backaction-driven control technique that has previously been considered a source of error. We benchmark our in-layer strategy, together with the standard FPGA-enabled approach, and analyse the performance of both methods using gate set tomography. Our results provide the first step towards moving resource-intensive classical processing into the quantum layer, an advance that could solve key engineering challenges, and drastically reduce the power budget of future quantum computers.
Abstract Among the many types of qubit presently being investigated for a future quantum computer, silicon spin qubits with millions of qubits on a single chip are uniquely positioned to enable quantum computing. However, it has not been clear whether the outstanding high-fidelity operations and long coherence times shown by silicon spin qubits fabricated in academic settings 1–8 can be reliably reproduced when the qubits are manufactured in a semiconductor foundry 9–11 . Here we show precise qubit operation of silicon two-qubit devices made with standard semiconductor tooling in a 300-mm foundry environment. Of the key metrics, single- and two-qubit control fidelities exceed 99% for all four devices, and the state preparation and measurement fidelities reach up to 99.9%, as evidenced by gate set tomography. We report spin lifetime and coherence up to T 1 = 9.5 s, T2∗=40.6 μs{T}_{2}^{* }=40.6\,{\rm{\mu }}{\rm{s}}T2∗​=40.6μs T 2 * = 40.6 μ s and T2Hahn=1.9 ms{T}_{2}^{{\rm{Hahn}}}=1.9\,{\rm{ms}}T2Hahn​=1.9ms T 2 Hahn = 1.9 ms . We determine that residual nuclear spin-carrying isotopes contribute substantially to operational errors, identifying further isotopic purification as a clear pathway to even higher performance.
The simplicity of encoding a qubit in the state of a single electron spin and the potential for their integration into industry-standard microchips continue to drive the field of semiconductor-based quantum computing. After a series of key first-principles demonstrations validating universal gate operations, initialization and readout, three-qubit algorithms have already been realized with silicon-based quantum dots in past years. Devices containing more qubits have become available since then but experiments have not gone beyond meeting the DiVincenzo criteria. In this work, we fully exploit the capacity of a spin-qubit array and implement a six-qubit quantum circuit, the largest utilizing semiconductor quantum technology. By programming the quantum processor, we execute quantum circuits across all permutations of three, four, five, and six neighboring qubits, demonstrating successful programmable multi-qubit operation throughout the array. Using an error model that incorporates quasi-static noise allows us to qualitatively explain some key trends in our experimental results and highlight the necessity to minimize idling times through simultaneous operations, extending dephasing times, and consistently improving state preparation and measurement fidelities.
Recent advances in coherent spin shuttling have made sparse semiconductor spin qubit arrays an appealing solid-state platform to realize quantum processors. The dynamic and long-range connectivity enabled by shuttling is also essential for many quantum error-correction (QEC) schemes. Here, we demonstrate a silicon spin-qubit device that comprises a shuttling bus for coherently transporting qubits that can interact at four isolated locations we call bus stops. We dynamically populate the array and tune all single- and two-qubit operations using shuttling and quantum non-demolition (QND) spin measurements, without access to charge sensing in most of the device. We achieve universal control of the effective five-qubit processor and select the connectivity required to form a surface-code stabilizer plaquette that supports X- and Z-type parity checks up to weight-four. We use the parity checks to generate multi-qubit entanglement between all qubit combinations in the array and report the genuine entanglement of a five-qubit Greenberger-Horne-Zeilinger (GHZ) state, constituting the largest such state ever constructed with gate-defined semiconductor spins. This work opens immediate opportunities to pursue QEC experiments with spin qubits, and the protocols developed here lay the groundwork for the modular calibration and operation of sparse spin qubit arrays.