How far are deployed quantum gates from the fastest evolution quantum mechanics allows? We answer for pre-Heron IBM processors, mainly Falcon and Eagle, using public, version-pinned calibration snapshots and inequalities whose proofs are machine-checked in Lean 4. Heron snapshots lack a Hamiltonian. For single-qubit gates, with the drive-strength convention fixed by IBM's calibrated π pulses, the X gate lasts a median 11.3 times the two-level speed limit at full drive amplitude (1646 qubits, 41 backends). Most of this gap is a design choice: IBM drives at about a tenth of the anharmonicity, and at that drive its pulses are about 2 times the square-pulse limit. Within each device's full amplitude, optimal control on IBM's model gives gates about 10 times faster than the median. For two-qubit gates (1758 coupled pairs, 43 backends), the known qubit-subspace minimal time of controlled-NOT-class gates under exchange coupling (literature) gives a median ratio 4.22; across the snapshots it rose, not monotonically, from 2.78 (2021) to 4.26 (2025) as gates got longer, coinciding with the change from Falcon to Eagle. With the second level and fast arbitrary local control, the minimal time of a controlled-Z gate with ideal local control lies between 0.287 and 1/3 of the qubit-only exchange time (refined bound, explicit construction); bounded local control reaches 0.35. We also formalize an entangling-time bound in arbitrary local dimension, known for qubits and new only as a machine-checked assembly. Applied to IBM's chip-to-chip state transfer (version 2), the same diagnostic places the transfers at 5.8--7.9 times the single-mode minimal time, whose lower bound is machine-checked in Isabelle, and the coherence error of the fastest protocol four to six times below the measured errors. The contribution is a reproducible diagnostic built on the machine-checked inequalities, with explicit guarantees. Companion site (blueprint): https://karlesmarin.github.io/blueprints/qsl-diagnostics/
How far are deployed quantum gates from the fastest evolution quantum mechanics allows? We answer for pre-Heron IBM processors, mainly Falcon and Eagle, using public, version-pinned calibration snapshots and inequalities whose proofs are machine-checked in Lean 4. Heron snapshots lack a Hamiltonian. For single-qubit gates, with the drive-strength convention fixed by IBM's calibrated π pulses, the X gate lasts a median 11.3 times the two-level speed limit at full drive amplitude (1646 qubits, 41 backends). Most of this gap is a design choice: IBM drives at about a tenth of the anharmonicity, and at that drive its pulses are about 2 times the square-pulse limit. Within each device's full amplitude, optimal control on IBM's model gives gates about 10 times faster than the median. For two-qubit gates (1758 coupled pairs, 43 backends), the known qubit-subspace minimal time of controlled-NOT-class gates under exchange coupling (literature) gives a median ratio 4.22; across the snapshots it rose, not monotonically, from 2.78 (2021) to 4.26 (2025) as gates got longer, coinciding with the change from Falcon to Eagle. With the second level and fast arbitrary local control, the minimal time of a controlled-Z gate with ideal local control lies between 0.287 and 1/3 of the qubit-only exchange time (refined bound, explicit construction); bounded local control reaches 0.35. We also formalize an entangling-time bound in arbitrary local dimension, known for qubits and new only as a machine-checked assembly. Applied to IBM's chip-to-chip state transfer (version 2), the same diagnostic places the transfers at 5.8--7.9 times the single-mode minimal time, whose lower bound is machine-checked in Isabelle, and the coherence error of the fastest protocol four to six times below the measured errors. The contribution is a reproducible diagnostic built on the machine-checked inequalities, with explicit guarantees. Companion site (blueprint): https://karlesmarin.github.io/blueprints/qsl-diagnostics/
Logic gates in superconducting quantum processors are implemented through precisely shaped microwave pulses, whose durations are constrained by both device coherence and the multilevel structure of artificial atoms. While single-qubit fidelities above 0.999 are routinely achieved, the physical execution time of these gates remains a major bottleneck for deep quantum circuits. Here we examine single-qubit control across adiabatic [where the rotating-wave approximation (RWA) is valid], intermediate, and diabatic driving regimes using both an ideal two-level model and a realistic weakly anharmonic transmon Hamiltonian. By sweeping pulse durations and drive strengths over experimentally relevant ranges, we compare performance trade-offs and identify the conditions under which ultrashort gates remain viable. Our simulations uncover a quantitative speed-limit mechanism intrinsic to weakly anharmonic superconducting qubits: leakage to higher levels rises sharply once the peak Rabi rate exceeds a fixed fraction of the anharmonicity. Across all pulse shapes and driving regimes studied, we find a consistent numerical threshold at Ω max /|Δ|≈0.15−0.20, where Ω max denotes the peak drive (Rabi) amplitude and Δ is the transmon anharmonicity. Beyond this ratio, gate fidelity deteriorates regardless of waveform engineering. This boundary, obtained from full multilevel time-domain simulations spanning adiabatic, intermediate, and diabatic regimes, constitutes a previously unreported characterization of the fundamental leakage barrier in transmon devices. Our results, therefore, provide the first unified quantitative map linking pulse duration, driving strength, and anharmonicity, establishing why realistic superconducting qubits cannot sustain picosecond-scale gates despite ideal two-level predictions, and offering a practical benchmark for next-generation architectures seeking shorter, high-fidelity control.
Quantum state readout on many experimental platforms is performed through a single projective measurement channel rather than full quantum state tomography. We derive a detector-conditioned quantum speed limit that constrains the minimum time for the projective fidelity F(t)=⟨ω∣ρ(t)∣ω⟩ to reach a prescribed discrimination threshold:T≥ΔHω∣Θ(0)−Θ∗∣,where Θ=arccosF is the Bures angle and ΔHω is the energy standard deviation of the \emph{fixed target state}. This bound, valid for both pure and mixed states under unitary dynamics, expresses the speed constraint in terms of a time-independent quantity determined entirely by the Hamiltonian and the detector projector, rather than the evolving-state variance appearing in standard Mandelstam--Tamm-type bounds. We further show that the resulting bound is structurally distinct from standard Mandelstam--Tamm-type bounds based on evolving-state variance. The bound exhibits commuting-sector invariance, suppressing Hamiltonian components that are energetically large but detection-irrelevant. Exact diagonalization of the transverse-field Ising model for N≤12 spins confirms asymptotic separation between the bounds in the strong-interaction regime. The framework provides a detector-conditioned lower bound for rank-1 projective detection dynamics, applicable to superconducting qubit readout, trapped-ion fluorescence detection, and stabilizer syndrome monitoring. The construction is particularly relevant for architectures in which experimentally accessible information is restricted to a small set of projective readout channels rather than full-state tomography. ## Results & Validation Below is the macro-level data extracted from the 156-qubit **ibm_fez** processor, confirming the asymptotic separation predicted by Theorem 5.2 as the many-body coupling strength scales extensively: [Quantum Speed Limit Validation Benchmark](qsl_validation_plot.png) ## Hardware Compilation Profile The transpiled circuit diagram below illustrates the native pulse-level gate routing on the IBM Quantum Heron architecture. By optimizing the physical register map, the compiler enforces a clean nearest-neighbor coupling loop with zero SWAP gate overhead: [Heron Chip Circuit Native Compilation](circuit-d8uhclsbp3hs73861d7g.png) ## Raw Measurement Diagnostics To evaluate the projective fidelity reduction threshold (F∗=0.15), raw binary distributions are unpacked and corrected using Matrix-Free Measurement Mitigation (M3). Below is a representative diagnostic histogram of single-outcome state frequencies sampled from the hardware backend: [Error Mitigated Hardware Measurement Histogram](job_d8uhc4ctqbtc73d1qdmg_results_c.png)
The speed of elementary quantum gates ultimately sets the limit on the speed at which quantum circuits can operate. For a fixed physical interaction strength between two qubits, the speed of any two-qubit gate is limited even with arbitrarily fast single-qubit gates. In this work, we explore the possibilities of speeding up two-qubit gates beyond such a limit by expanding our computational space outside the qubit subspace, which is experimentally relevant for qubits encoded in multi-level atoms or anharmonic oscillators. We identify an optimal theoretical bound for the speed limit of a two-qubit gate achieved using two qudits with a bounded interaction strength and arbitrarily fast single-qudit gates. In addition, we find an experimentally feasible protocol using two parametrically coupled superconducting transmons that achieves this theoretical speed limit in a non-trivial way. We also consider practical scenarios with limited single-qudit drive strengths and off-resonant transitions. For such scenarios, we develop an open-source, machine learning assisted, quantum optimal control algorithm that can achieve a speedup close to the theoretical limit with near-perfect gate fidelity. This work opens up a new avenue to speed up two-qubit gates when the physical interaction strength between qubits cannot be easily increased while extra states outside the qubit subspace can be well controlled.
The speed of quantum evolution is limited under finite energy resources. While most quantum speed limits (QSLs) are formulated in terms of quantum states, they can be extended to the evolution operator itself, and thus impose fundamental limits on how quickly logical gate operations can be implemented on a quantum computer. Here, we derive a general, tight QSL that holds for any unitary evolution under the constraint that the spectral width of the Hamiltonian is bounded. We apply this result to obtain QSLs for several standard quantum gates, including Hadamard, CNOT, and Toffoli gates, finding that the QSL can vary significantly across different gates, including ones with the same entangling power. These findings can be understood geometrically using the Space Curve Quantum Control formalism, which maps unitary evolution to space curves in Euclidean space. In this formalism, the problem of finding QSLs is recast as the problem of finding minimal-length curves obeying a curvature bound. We find that time-optimal gates map to helices of varying dimensions, and that QSLs can be understood from the perspective of a bottleneck principle in which the operator that evolves the slowest governs the minimal gate time.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
The speed of elementary quantum gates, particularly two-qubit gates, ultimately sets the limit on the speed at which quantum circuits can operate. In this work, we experimentally demonstrate commonly used two-qubit gates at nearly the fastest possible speed allowed by the physical interaction strength between two superconducting transmon qubits. We achieve this quantum speed limit by implementing experimental gates designed using a machine-learning-inspired optimal control method. Importantly, our method only requires the single-qubit drive strength to be moderately larger than the interaction strength to achieve an arbitrary two-qubit gate close to its analytical speed limit with high fidelity. Thus the method is applicable to a variety of platforms, including those with comparable single-qubit and two-qubit gate speeds, or those with always-on interactions. We expect our method to offer significant speedups for non-native two-qubit gates that are typically achieved with a long sequence of single-qubit and native two-qubit gates.