TARGET-VARIANCE QUANTUM SPEED LIMITS FROM PROJECTIVE FIDELITY REDUCTION
Roy Surya Sekhar
Abstract
Quantum state readout on many experimental platforms is performed through a single projective measurement channel rather than full quantum state tomography. We derive a detector-conditioned quantum speed limit that constrains the minimum time for the projective fidelity $F(t) = \langle\omega|\rho(t)|\omega\rangle$ to reach a prescribed discrimination threshold:\[T \;\ge\; \frac{|\Theta(0) - \Theta_*|}{\Delta H_\omega},\]where $\Theta = \arccos\sqrt{F}$ is the Bures angle and $\Delta H_\omega$ is the energy standard deviation of the \emph{fixed target state}. This bound, valid for both pure and mixed states under unitary dynamics, expresses the speed constraint in terms of a time-independent quantity determined entirely by the Hamiltonian and the detector projector, rather than the evolving-state variance appearing in standard Mandelstam--Tamm-type bounds. We further show that the resulting bound is structurally distinct from standard Mandelstam--Tamm-type bounds based on evolving-state variance. The bound exhibits commuting-sector invariance, suppressing Hamiltonian components that are energetically large but detection-irrelevant. Exact diagonalization of the transverse-field Ising model for $N \le 12$ spins confirms asymptotic separation between the bounds in the strong-interaction regime. The framework provides a detector-conditioned lower bound for rank-1 projective detection dynamics, applicable to superconducting qubit readout, trapped-ion fluorescence detection, and stabilizer syndrome monitoring. The construction is particularly relevant for architectures in which experimentally accessible information is restricted to a small set of projective readout channels rather than full-state tomography. ## Results & Validation Below is the macro-level data extracted from the 156-qubit **ibm_fez** processor, confirming the asymptotic separation predicted by Theorem 5.2 as the many-body coupling strength scales extensively: [Quantum Speed Limit Validation Benchmark](qsl_validation_plot.png) ## Hardware Compilation Profile The transpiled circuit diagram below illustrates the native pulse-level gate routing on the IBM Quantum Heron architecture. By optimizing the physical register map, the compiler enforces a clean nearest-neighbor coupling loop with zero SWAP gate overhead: [Heron Chip Circuit Native Compilation](circuit-d8uhclsbp3hs73861d7g.png) ## Raw Measurement Diagnostics To evaluate the projective fidelity reduction threshold ($F_* = 0.15$), raw binary distributions are unpacked and corrected using Matrix-Free Measurement Mitigation (M3). Below is a representative diagnostic histogram of single-outcome state frequencies sampled from the hardware backend: [Error Mitigated Hardware Measurement Histogram](job_d8uhc4ctqbtc73d1qdmg_results_c.png)
