H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
Quantum hardware remains highly susceptible to noise, making compilation a critical step for obtaining reliable execution on existing devices. Today's quantum compilers approximate hardware noise using calibration-derived costs over gates, qubits, and coupling edges, and use the costs to guide qubit mapping, routing, and scheduling. However, this abstraction is incomplete: semantically equivalent circuits with identical compiler-predicted hardware noise can still behave very differently on real devices. Execution context can contribute to this gap: short ordered gate sequences on specific qubit neighborhoods can be associated with hardware-model mismatch. Identifying these backend-dependent abnormal patterns can guide gate-ordering rewrites in the circuit family and layout where they were observed. To find these patterns, we propose QRisk, a framework that isolates recurring abnormal gate sequences from quantum hardware executions. QRisk starts from a circuit whose hardware output is much worse than predicted by the calibration-based noise model. It then reduces the circuit at the segment level, identifying groups of segments whose removal lowers the discrepancy ratio or whose retention within the tested circuit context preserves an elevated ratio. The resulting circuit fragments are treated as candidate abnormal patterns. On three IBM Heron r2 backends (quantum devices) across 30 qubit layouts, QRisk finds 25 recurring abnormal gate patterns. Reordering commuting gates to break the two highest-recurrence patterns in their Grover discovery circuits reduces mean hardware-model mismatch by 24% on ibm_fez and 45% on ibm_marrakesh.
Quantum processors have crossed the one-hundred-qubit mark, but noise continues to limit circuit performance, while full quantum error correction remains too costly for routine use. Error suppression and mitigation therefore play an important role in extracting value from current hardware, yet independent comparisons of commercial solutions on identical workloads and devices remain scarce. We benchmark IBM Qiskit Runtime, Q-CTRL Performance Management, and Qedma QESEM on IBM Pittsburgh, a 156-qubit IBM Quantum Heron r3 processor. For Sampler workloads, we run Bernstein-Vazirani, quantum phase estimation, GHZ-state preparation, and randomized mirror circuits with up to 100 measured qubits, comparing raw execution, IBM measurement twirling, and Q-CTRL. For Estimator workloads, we measure chain-averaged magnetization and correlation observables of an eight-layer transverse-field Ising circuit at 25, 50, and 75 qubits against an exact matrix-product-state reference, comparing IBM raw execution, IBM TREX plus twirling, Q-CTRL, and QESEM. Q-CTRL produced the best results on the three structured Sampler workloads while keeping reported QPU times within the same order as the IBM configurations. Across six Ising observable and system-size cases, aggregate mean absolute error was 0.0883 for IBM raw execution, 0.0807 for IBM TREX plus twirling, 0.0285 for Q-CTRL, and 0.0188 for QESEM. Relative to raw execution, Q-CTRL and QESEM reduced aggregate error by factors of 3.10 and 4.70, respectively, while QESEM used 7.5 to 11.1 times the reported QPU time of Q-CTRL. These results show that managed error suppression and mitigation can substantially improve current hardware performance, but with distinct accuracy and execution-time tradeoffs.
Qubit layout selection determining which physical qubits a logical circuit occupies on a superconducting processor is fundamentally a noise-field sampling problem. On IBM Heron r1 and Heron r2 devices, two-qubit gate error varies by nearly one order of magnitude (7– $9\times $ ) across qubit pairs on the same chip, causing measured fidelity differences up to 0.903 from layout choice alone. We introduce the Gate Noise Sensitivity Index (GNSI), a calibration-weighted linear combination of per-qubit readout error and per-edge two-qubit gate error, derived analytically as a first-order approximation of circuit fidelity under independent, heterogeneous noise channels. For 12 backend–circuit combinations on three IBM processors (133-qubit Heron r1 and 156-qubit Heron r2), GNSI scores are computed for the full pool of 1,320 computationally enumerated candidate layouts; the top-ranked (GNSI-BEST) and bottom-ranked (GNSI-WORST) layouts are then executed on hardware. GNSI-BEST ranks first by score in all 12 instances (Hit@1 = 100% within the enumerated candidate pool) and consistently achieves higher measured fidelity than GNSI-WORST, with Spearman rank correlation ρ=0.926±0.016 and statistically significant fidelity separation in 9 of 12 paired tests. Initial hardware comparisons on ibm_fez ( n=5 ) show GNSI-BEST matching or exceeding SABRE-selected fidelity. We further identify a depth-dependent regime transition: gate-error heterogeneity appears to govern ranking in shallow circuits (depth ≤15 ), while qubit-specific T1 variation may dominate for deeper circuits (depth ≥20 ). The analytic regime boundary d∗(b) , computable from calibration data alone, shows agreement within ±2 depth layers across all three backends in initial comparisons; GNSI-Extended incorporating the decoherence term receives an initial hardware comparison on two circuits, with full validation left to future work. These results suggest that layout-dependent fidelity variation may be governed by a calibration-predictable noise field, with direct implications for compiler design and noise-adaptive quantum circuit execution.
Quantum processors are now used as feature generators for classical models on tabular data. A circuit encodes each record, the device returns expectation values, and a classical model learns from them. A recent report claimed large gains from such features, gains that appeared only on noisy hardware. These claims are hard to check, because a quantum device is not a static function. Its state changes from job to job and from one calibration to the next, and that drift can leak information about the outcome into the features. We propose a five-step protocol for testing claims of this kind. It runs a circuit that carries no data in the same jobs as the real one. It checks whether the hardware leaves a recognizable mark on each job. It compares random and natural assignments of records to jobs, replays the null results under other submission orders, and closes the leak with a job-purged backtest. We apply it, pre-registered, to the HSBC and IBM study of fill probabilities in bond trading, which reported a large hardware-only gain. We use a public analog task and run the study's circuit on a 129-qubit chain of an IBM Heron processor. Under controlled assignment the hardware features give no gain over classical features, and the device reproduces the ideal features about as well as shot noise allows. Yet every job carries a distinct fingerprint. A circuit with no data at all predicts fills well above chance when records are batched by outcome and the same job sits on both sides of the train/test split. Removing that overlap removes the effect. The protocol costs under an hour of processor time and is designed for any hardware feature or kernel pipeline on tabular data.
Validating quantum processors at scale increasingly relies on approximate classical simulation, which adds truncation error to the comparison between ideal and observed behavior. We describe a 15-qubit dynamic-circuit benchmark that stays within exact state-vector simulation, so the ideal reference value is computed without approximation. The circuit scrambles a 6-qubit system, couples it to a 5-qubit engineered environment, reads out four weakly coupled probe qubits mid-circuit, and then applies the inverse of the scrambling and system–environment coupling to restore the system's coherence. Exact summation over the 16 probe outcomes gives an ideal recovery fidelity F_max = 0.9889 on the 11-qubit system–environment register; the shortfall from unity reflects information carried away by the probes, whose coupling is not inverted and which are discarded after readout. We demonstrate the pipeline with a single 400-shot run on the Quantinuum H2-1 emulator (quantinuum.sim.h2-1e) via Azure Quantum. A local surrogate built from three published H2-1 headline error rates predicted F_exp = 0.8353 ± 0.0054; the emulator returned a readout-mitigated F_rec = 0.7836 ± 0.0212, 2.36 nominal standard errors lower. Because the surrogate's quoted uncertainty reflects sampling error only, we interpret the shortfall as evidence of surrogate-model mismatch—expected, given the emulator's richer noise model—rather than as a statistically calibrated anomaly. No physical-hardware data are reported. Changes in v50: Retitled (formerly "A 15-Qubit Decoherence-Reversal Protocol for Benchmarking Mid-Circuit Measurements and Environmental Imprinting"). Corrected the echo formulation (v49 Eq. 4 was identically 1) and the reported raw frequency (77.5%, not 76.0%). Result reframed as a nominal surrogate-model mismatch on the H2-1 emulator rather than anomalous decoherence; SWAP-routing explanation withdrawn. References corrected; limitations and data/code availability added. Analysis code unchanged from v48. Code and data: https://github.com/dkahng/15-qubit-mcm-protocol
We report a set of pre-registered experiments on the three 156-qubit IBM Heron r2 processors reachable on a single open-plan account (ibm_kingston, ibm_marrakesh, ibm_fez), carried out on 14–15 October 2026. The object of study is not computational speedup but channel reliability: whether fixed symbolic messages can be delivered intact through a present-day noisy processor when the processor's per-wire readout response is measured fresh in the same sitting, and whether two such processors can exchange messages with per-position verification. Messages are 17-symbol sequences drawn from a 13-symbol test alphabet whose preparations collapse to nine distinguishable readout classes. A receiver combining per-wire selection from a fresh characterization, grammar-constrained decoding, and a corpus-frequency tie-break delivered 36/36 messages on ibm_kingston in two independent campaigns, 36/36 on ibm_marrakesh, and 35/36 on ibm_fez, against stale-plan and uncharacterized controls ranging from 2/36 to 30/36 depending on backend and control type. The grammar-constrained receiver without the corpus prior scored 30/36, 30/36, and 29/36 on the three backends; its losses are a single systematic mechanism — a deterministic tie on one battery message — identified from saved counts and closed by the prior. In a separate experiment, ibm_kingston and ibm_marrakesh exchanged self-introduction streams authored by each backend from its own fresh characterization, through a six-stage symmetric relay, with 204/204 position-flights received exactly and zero substitutions. In a counts-only blind test, an independent decoder with no shared codebook recovered the discreteness and grouping structure of two authored streams (pooled pairwise grouping agreement 0.971 against a pre-registered 0.90 strong-pass bar) while overestimating the alphabet size (reported 8, true value 6). A census of repeated characterizations shows that the ranking of a device's clearest wires turns over within hours (same-day top-17 wire overlap of 1–2 of 17 on ibm_marrakesh), while per-wire response quality moves by only ~0.01, so characterizations are within-sitting instruments. No speedup, no machine networking, and no machine understanding is claimed. The full receiver implementation is withheld as a trade secret; verification is offered through the published job IDs, retained raw counts, and tiered third-party reproduction.