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IEEE Access

Noise-Field Sampling and Regime Transitions in Qubit Layout Selection: Hardware Evidence on IBM Superconducting Processors

Saripudi Suneetha, Kakumani K. C. Deepthi

Published Jan 1, 2026• 0 citations
Publisher

Abstract

Qubit layout selection determining which physical qubits a logical circuit occupies on a superconducting processor is fundamentally a noise-field sampling problem. On IBM Heron r1 and Heron r2 devices, two-qubit gate error varies by nearly one order of magnitude (7– $9\times $ ) across qubit pairs on the same chip, causing measured fidelity differences up to 0.903 from layout choice alone. We introduce the Gate Noise Sensitivity Index (GNSI), a calibration-weighted linear combination of per-qubit readout error and per-edge two-qubit gate error, derived analytically as a first-order approximation of circuit fidelity under independent, heterogeneous noise channels. For 12 backend–circuit combinations on three IBM processors (133-qubit Heron r1 and 156-qubit Heron r2), GNSI scores are computed for the full pool of 1,320 computationally enumerated candidate layouts; the top-ranked (GNSI-BEST) and bottom-ranked (GNSI-WORST) layouts are then executed on hardware. GNSI-BEST ranks first by score in all 12 instances (Hit@1 = 100% within the enumerated candidate pool) and consistently achieves higher measured fidelity than GNSI-WORST, with Spearman rank correlation $\rho = 0.926 \pm 0.016$ and statistically significant fidelity separation in 9 of 12 paired tests. Initial hardware comparisons on ibm_fez ( $n=5$ ) show GNSI-BEST matching or exceeding SABRE-selected fidelity. We further identify a depth-dependent regime transition: gate-error heterogeneity appears to govern ranking in shallow circuits (depth $\leq 15$ ), while qubit-specific $T_{1}$ variation may dominate for deeper circuits (depth $\geq 20$ ). The analytic regime boundary $d^{*}(b)$ , computable from calibration data alone, shows agreement within ±2 depth layers across all three backends in initial comparisons; GNSI-Extended incorporating the decoherence term receives an initial hardware comparison on two circuits, with full validation left to future work. These results suggest that layout-dependent fidelity variation may be governed by a calibration-predictable noise field, with direct implications for compiler design and noise-adaptive quantum circuit execution.

DOI
10.1109/access.2026.3716117

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Qubit layout selection determining which physical qubits a logical circuit occupies on a superconducting processor is fundamentally a noise-field sampling problem. On IBM Heron r1 and Heron r2 devices, two-qubit gate error varies by nearly one order of magnitude (7– 9×9\times 9× ) across qubit pairs on the same chip, causing measured fidelity differences up to 0.903 from layout choice alone. We introduce the Gate Noise Sensitivity Index (GNSI), a calibration-weighted linear combination of per-qubit readout error and per-edge two-qubit gate error, derived analytically as a first-order approximation of circuit fidelity under independent, heterogeneous noise channels. For 12 backend–circuit combinations on three IBM processors (133-qubit Heron r1 and 156-qubit Heron r2), GNSI scores are computed for the full pool of 1,320 computationally enumerated candidate layouts; the top-ranked (GNSI-BEST) and bottom-ranked (GNSI-WORST) layouts are then executed on hardware. GNSI-BEST ranks first by score in all 12 instances (Hit@1 = 100% within the enumerated candidate pool) and consistently achieves higher measured fidelity than GNSI-WORST, with Spearman rank correlation ρ=0.926±0.016\rho = 0.926 \pm 0.016ρ=0.926±0.016 and statistically significant fidelity separation in 9 of 12 paired tests. Initial hardware comparisons on ibm_fez ( n=5n=5n=5 ) show GNSI-BEST matching or exceeding SABRE-selected fidelity. We further identify a depth-dependent regime transition: gate-error heterogeneity appears to govern ranking in shallow circuits (depth ≤15\leq 15≤15 ), while qubit-specific T1T_{1}T1​ variation may dominate for deeper circuits (depth ≥20\geq 20≥20 ). The analytic regime boundary d∗(b)d^{*}(b)d∗(b) , computable from calibration data alone, shows agreement within ±2 depth layers across all three backends in initial comparisons; GNSI-Extended incorporating the decoherence term receives an initial hardware comparison on two circuits, with full validation left to future work. These results suggest that layout-dependent fidelity variation may be governed by a calibration-predictable noise field, with direct implications for compiler design and noise-adaptive quantum circuit execution.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
Despite rapid progress in quantum optimization, broad real-hardware benchmarks comparing multiple algorithmic families across diverse combinatorial problems under a common protocol remain limited. We benchmark gate-based quantum optimization on four NP-hard problems: multi-dimensional knapsack (MDKP), maximum independent set (MIS), quadratic assignment (QAP), and market-share (MSP). We study VQE, CVaR-VQE, standard, multi-angle, and warm-start QAOA, together with qubit-efficient PCE and QRAO, on IBM Heron r1/r2 processors using resilience-level-2 mitigation. To our knowledge, this includes the first real-hardware QRAO results and the first multi-problem PCE hardware benchmark. Across 247 method-instance combinations, we report transpiled circuit size, hardware outcomes, and an independent-error gate-count fidelity proxy, FestF_{\mathrm{est}}Fest​. For MDKP and MIS, an empirical operating point near Fest≈0.1F_{\mathrm{est}}\approx 0.1Fest​≈0.1, corresponding to about 770 two-qubit gates at the median Heron-r2 CZ error rate, marks the onset of noise-dominated execution. QAP exposes a separate bottleneck: dense one-hot encodings and an exponentially sparse feasible manifold, with feasible fraction 10!/210010!/2^{100}10!/2100 at n=10n=10n=10; no tested hardware method produces a feasible assignment. Compiled QAOA-family circuits are generally noise dominated, and a matched uniform-random control shows that most feasible low-fidelity outcomes fall within the random range, apart from one finite-sample MIS warm-start exception. A SWAP-aware, fractional-gate, Nighthawk-topology compilation counterfactual reduces two-qubit counts but leaves all circuits below Fest=10−3F_{\mathrm{est}}=10^{-3}Fest​=10−3. These conclusions apply to the tested implementations rather than QAOA in general. Qubit-efficient methods extend runnable instance sizes, but only within the empirical fidelity budget.
We present an empirical study of circuit-depth thresholds on IBM Quantum Heron-class hardware using 4- and 5-qubit GHZ-state preparation circuits with logical depths from 2 to 20. On ibm_torino, we observe qubit-count-dependent depth limits: 4-qubit circuits reach a fidelity plateau near 88% beyond depth 10, while 5-qubit circuits show continued decay from 89.4% to 83.7% over the same range. The observed fidelity at depth 20 substantially exceeds predictions from an independent gate-error model (88% vs. 61%), indicating coherent error effects and partial error cancellation not captured by simple accumulation models. These results provide hardware-specific depth bounds for near-term quantum circuits and support calibration-based depth selection over fixed heuristics. We recommend a maximum depth ≤ 10 for applications requiring >85% fidelity on this hardware.
The practical utility of Noisy Intermediate-Scale Quantum (NISQ) processors depends critically on their performance under demanding computational loads. We investigated the impact of circuit depth on the 127-qubit superconducting processor ibm_brisbane by executing stress-test circuits utilizing all available qubits. These circuits consisted of repeated layers combining random single-qubit rotations and linear chains of Controlled-Z entangling gates. We systematically increased the ideal circuit depth from 1 up to 30 layers, resulting in transpiled circuits ranging from approximately 550 to over 15,000 gates (optimization level 2). Using the qiskit-ibm-runtime Sampler primitive with 4096 shots and default error mitigation, we successfully obtained results for ideal depths up to 22 (transpiled depth ~11.7k gates), beyond which platform usage limits prevented execution. Our central finding is the immediate onset of noise saturation: the output distribution reached maximum sample entropy (12.0 bits) and exhibited near-zero average single-qubit Z magnetization even at the shallowest depth tested (ideal depth 1, transpiled depth ~550). These noise-dominated characteristics persisted despite significant increases in transpiled circuit depth. This demonstrates that for these specific full-width, complex random circuits, noise overwhelms the computation almost instantaneously on this device under default settings, highlighting the profound challenge of achieving computational fidelity for deep, wide algorithms in the NISQ era without advanced error handling.
Achieving high-fidelity execution on noisy intermediate-scale quantum (NISQ) hardware requires careful selection of physical qubit layouts, as gate errors, readout errors, and coherence times vary across the device and drift over time. Currently, qubit mapping is performed either through manual inspection of device calibration data or through automated layout pipelines, neither of which provides integrated, interactive layout visualization combined with calibration analytics. In this work, we present the Interactive Quantum Mapper (I-QMapper), a Jupyter-based, open-source tool for noise-aware layout selection, visualization, and analysis on superconducting quantum hardware. I-QMapper offers two operating modes: a general-purpose mode for arbitrary circuits, and a dedicated mode for quantum-chemistry applications, specifically tailored to the Local Unitary Cluster Jastrow (LUCJ) ansatz. Within each mode, a Design panel supports interactive layout construction, while an Error panel provides calibration analytics through four temporal viewing modes (Live, Snapshot, Intraday, and Multi-day range) together with threshold filtering and delta-mode comparison for drift identification. Each layout receives a Layout-Quality Score (LQS) that aggregates the readout and two-qubit gate errors of the layout into a single quality value. Starting from the automatic LUCJ circuit-generation provided by IBM Quantum, we extend it to a multi-programming setting in which multiple circuits are mapped onto a single quantum processing unit (QPU). I-QMapper further supports side-by-side visualization of two quantum backends and layout comparison, and session export for experimental reproducibility. By combining interactive exploration with calibration analytics, I-QMapper aims to support both rapid layout prototyping and informed noise-aware experimental design on NISQ devices.
The practical utility of Noisy Intermediate-Scale Quantum (NISQ) processors depends critically on their performance under demanding computational loads. We investigated the impact of circuit depth on the 127-qubit superconducting processor ibm_brisbane by executing stress-test circuits utilizing all available qubits. These circuits consisted of repeated layers combining random single-qubit rotations and linear chains of Controlled-Z entangling gates. We systematically increased the ideal circuit depth from 1 up to 30 layers, resulting in transpiled circuits ranging from approximately 550 to over 15,000 gates (optimization level 2). Using the qiskit-ibm-runtime Sampler primitive with 4096 shots and default error mitigation, we successfully obtained results for ideal depths up to 22 (transpiled depth ~11.7k gates), beyond which platform usage limits prevented execution. Our central finding is the immediate onset of noise saturation: the output distribution reached maximum sample entropy (12.0 bits) and exhibited near-zero average single-qubit Z magnetization even at the shallowest depth tested (ideal depth 1, transpiled depth ~550). These noise-dominated characteristics persisted despite significant increases in transpiled circuit depth. This demonstrates that for these specific full-width, complex random circuits, noise overwhelms the computation almost instantaneously on this device under default settings, highlighting the profound challenge of achieving computational fidelity for deep, wide algorithms in the NISQ era without advanced error handling.