We present an empirical study of circuit-depth thresholds on IBM Quantum Heron-class hardware using 4- and 5-qubit GHZ-state preparation circuits with logical depths from 2 to 20. On ibm_torino, we observe qubit-count-dependent depth limits: 4-qubit circuits reach a fidelity plateau near 88% beyond depth 10, while 5-qubit circuits show continued decay from 89.4% to 83.7% over the same range. The observed fidelity at depth 20 substantially exceeds predictions from an independent gate-error model (88% vs. 61%), indicating coherent error effects and partial error cancellation not captured by simple accumulation models. These results provide hardware-specific depth bounds for near-term quantum circuits and support calibration-based depth selection over fixed heuristics. We recommend a maximum depth ≤ 10 for applications requiring >85% fidelity on this hardware.
We present an empirical study of circuit-depth thresholds on IBM Quantum Heron-class hardware using 4- and 5-qubit GHZ-state preparation circuits with logical depths from 2 to 20. On ibm_torino, we observe qubit-count-dependent depth limits: 4-qubit circuits reach a fidelity plateau near 88% beyond depth 10, while 5-qubit circuits show continued decay from 89.4% to 83.7% over the same range. The observed fidelity at depth 20 substantially exceeds predictions from an independent gate-error model (88% vs. 61%), indicating coherent error effects and partial error cancellation not captured by simple accumulation models. These results provide hardware-specific depth bounds for near-term quantum circuits and support calibration-based depth selection over fixed heuristics. We recommend a maximum depth ≤ 10 for applications requiring >85% fidelity on this hardware.
Qubit layout selection determining which physical qubits a logical circuit occupies on a superconducting processor is fundamentally a noise-field sampling problem. On IBM Heron r1 and Heron r2 devices, two-qubit gate error varies by nearly one order of magnitude (7– $9\times $ ) across qubit pairs on the same chip, causing measured fidelity differences up to 0.903 from layout choice alone. We introduce the Gate Noise Sensitivity Index (GNSI), a calibration-weighted linear combination of per-qubit readout error and per-edge two-qubit gate error, derived analytically as a first-order approximation of circuit fidelity under independent, heterogeneous noise channels. For 12 backend–circuit combinations on three IBM processors (133-qubit Heron r1 and 156-qubit Heron r2), GNSI scores are computed for the full pool of 1,320 computationally enumerated candidate layouts; the top-ranked (GNSI-BEST) and bottom-ranked (GNSI-WORST) layouts are then executed on hardware. GNSI-BEST ranks first by score in all 12 instances (Hit@1 = 100% within the enumerated candidate pool) and consistently achieves higher measured fidelity than GNSI-WORST, with Spearman rank correlation ρ=0.926±0.016 and statistically significant fidelity separation in 9 of 12 paired tests. Initial hardware comparisons on ibm_fez ( n=5 ) show GNSI-BEST matching or exceeding SABRE-selected fidelity. We further identify a depth-dependent regime transition: gate-error heterogeneity appears to govern ranking in shallow circuits (depth ≤15 ), while qubit-specific T1 variation may dominate for deeper circuits (depth ≥20 ). The analytic regime boundary d∗(b) , computable from calibration data alone, shows agreement within ±2 depth layers across all three backends in initial comparisons; GNSI-Extended incorporating the decoherence term receives an initial hardware comparison on two circuits, with full validation left to future work. These results suggest that layout-dependent fidelity variation may be governed by a calibration-predictable noise field, with direct implications for compiler design and noise-adaptive quantum circuit execution.
The Quantum Approximate Optimization Algorithm (QAOA) is a leading candidate for near-term quantum advantage in combinatorial optimization. A central design parameter is circuit depth p, with theoretical analyses establishing asymptotic convergence under idealized conditions. This paper presents a limits study demonstrating that this theoretical relationship does not translate to measurable improvement on current noisy intermediate-scale quantum (NISQ) hardware for fault tree analysis applications. Across 120 QAOA executions on 60 QUBO-encoded fault tree instances (N ∈ {12, 16, 20, 24, 28, 32}) on IBM Quantum hardware (ibm_torino, 133-qubit Heron processor), circuit depths p = 1 and p = 2 were directly compared. The mean change in optimal state sampling probability from doubling circuit depth was Δmax_prob = 1.22 × 10⁻⁵ with a median Δ of zero. For 8,192 shots, the binomial sampling uncertainty is O(10⁻²); the observed mean delta is therefore approximately three orders of magnitude below the shot-noise scale, making the difference statistically indistinguishable from zero. Output distribution entropy approaches the theoretical maximum of log₂(8192) ≈ 13 bits, indicating hardware noise dominates algorithmic signal. These findings establish that for fault tree minimal cut set identification on current NISQ devices, computational resources are more effectively allocated to increased shot counts than to circuit depth. Complete experimental artifacts with SHA-256 verification are provided, enabling full reproducibility.
This paper presents a noise-scaled simulation study to characterize whether increased QAOA circuit depth provides measurable improvement for fault tree QUBO instances under varying two-qubit gate fidelity conditions. Using 60 fault tree instances with circuits loaded via QPY serialization, we executed 960 simulations spanning depths p = 1 and p = 2 across a fidelity sweep from F₂ = 0.900 to F₂ = 0.992, with fixed single-qubit fidelity F₁ = 0.9995 and readout fidelity Fro = 0.97. The primary finding is that output distributions are noise-dominated and shot-limited at all tested fidelity levels. Maximum probability values cluster near the shot floor of 1/1024, and Shannon entropy approaches the measurement ceiling of 10 bits. The median difference between depth p = 2 and depth p = 1 is exactly zero for maximum probability at all fidelity levels. No consistent improvement in distribution concentration is observed as fidelity increases within the tested range. These results establish that no depth benefit is detectable through F₂ = 0.992 under this noise model and shot budget. Practitioners should not expect depth scaling to improve output quality until gate fidelity exceeds the upper bound of this sweep. This completes the investigation arc from prior work: depth does not help on current hardware because noise accumulation exceeds algorithmic signal, and this finding persists through the tested fidelity range.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
The development of complex circuits for practical applications in the current quantum computing ecosystem is based on basic primitives such as Bell states, which provide superposition, entanglement, and coherence. The range of domain-specific quantum applications has been greatly expanded by the availability of simulators and platforms such as IBM Quantum, which are supported by Qiskit. However, disparities between ideal simulator outputs and actual quantum processing unit (QPU) executions in the Noisy Intermediate-Scale Quantum (NISQ) era require the application of quantum error mitigation techniques. Limitations arise from hardware constraints in superconducting qubit systems and from the limited resources of classical simulators as quantum circuits grow. Quantum decoherence, which lowers gate fidelity and builds up at the circuit level with increasing depth, is specifically caused by material-induced flaws and interfaces. This creates a clear connection between circuit reliability, device performance, and material attributes. To address this, the current work uses both simulation and actual hardware on the IBM Sherbrooke 127-qubit processor to study three basic circuit classes over 4 to 10 qubits: the quantum Fourier transform, the Greenberger-Horne-Zeilinger state, and the W state. The study examines trade-offs between circuit complexity, noise robustness, and resource utilization by contrasting simulator and QPU results. The results imply that circuit fidelity can serve as an indirect probe of material-limited noise, opening the door to a framework for designing quantum circuits that accounts for both hardware and materials to achieve scalable quantum advantage.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.