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arXiv:2610.41268

Testing hardware quantum machine learning claims with a null circuit: fill prediction on Binance futures with 129 qubits of an IBM Heron processor

Muhammad Faryad

quant-phSubmitted Oct 30, 2026• Announced Nov 2, 2026
arXivHTMLPDF

Abstract

Quantum processors are now used as feature generators for classical models on tabular data. A circuit encodes each record, the device returns expectation values, and a classical model learns from them. A recent report claimed large gains from such features, gains that appeared only on noisy hardware. These claims are hard to check, because a quantum device is not a static function. Its state changes from job to job and from one calibration to the next, and that drift can leak information about the outcome into the features. We propose a five-step protocol for testing claims of this kind. It runs a circuit that carries no data in the same jobs as the real one. It checks whether the hardware leaves a recognizable mark on each job. It compares random and natural assignments of records to jobs, replays the null results under other submission orders, and closes the leak with a job-purged backtest. We apply it, pre-registered, to the HSBC and IBM study of fill probabilities in bond trading, which reported a large hardware-only gain. We use a public analog task and run the study's circuit on a 129-qubit chain of an IBM Heron processor. Under controlled assignment the hardware features give no gain over classical features, and the device reproduces the ideal features about as well as shot noise allows. Yet every job carries a distinct fingerprint. A circuit with no data at all predicts fills well above chance when records are batched by outcome and the same job sits on both sides of the train/test split. Removing that overlap removes the effect. The protocol costs under an hour of processor time and is designed for any hardware feature or kernel pipeline on tabular data.

AI Summary

The paper asks whether gains from quantum-hardware features in tabular machine learning can arise from job-dependent device drift rather than input-dependent information. Motivated by HSBC/IBM’s reported bond-fill prediction gains, it proposes five checks: interleaved data-independent null circuits, job-identification tests, randomized versus natural record assignment, replay of null outputs under alternative submission orders, and backtests excluding training records that share hardware jobs with test records. The experiment uses 1,000 public Binance futures events, 216 classical features, and a 129-qubit Heisenberg feature circuit on IBM Heron, with 3,072 CZ gates and 1,024 shots per measurement basis. Under randomized assignment, hardware features achieve AUC 0.570 versus 0.583 classically; the paired difference is $-0.013$, with 95% interval $[-0.075,0.047]$. Natural chronological assignment and null circuits show no gain. Hardware features retain approximately 62% of ideal variation, with hardware–ideal correlation 0.39 versus a shot-noise ceiling of 0.42. Null outputs identify hardware jobs perfectly despite small per-feature offsets. Reassigning them to outcome-sorted batches yields AUC 0.778, falling to 0.514 after job purging. This demonstrates a sufficient leakage mechanism, not its occurrence in HSBC’s private pipeline. Limitations include one task, circuit family and device; an analog rather than the original dataset; fewer events and shots; and narrower model searches. The analysis plan was internally frozen before execution but not externally timestamped until publication; two procedural deviations are disclosed.

No sign of AI-generated textAI use disclosed
The author used Claude (Anthropic), an AI assistant, to help write and test the analysis code and to edit the manuscript.

Error found: The claimed pre-registration has no independently verifiable pre-run timestamp, because its hash and frozen files were disclosed only at publication. The categorical statement that hardware features give no gain exceeds the statistical evidence, which excludes the prespecified gain threshold for the primary comparison but still permits smaller benefits.

Written by gpt-6.1-sol from the paper's full text. Automated: it can be wrong.

Comments
15 pages, 8 figures

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Quantum processors are now used as feature generators for classical models on tabular data. A circuit encodes each record, the device returns expectation values, and a classical model learns from them. A recent report claimed large gains from such features, gains that appeared only on noisy hardware. These claims are hard to check, because a quantum device is not a static function. Its state changes from job to job and from one calibration to the next, and that drift can leak information about the outcome into the features. We propose a five-step protocol for testing claims of this kind. It runs a circuit that carries no data in the same jobs as the real one. It checks whether the hardware leaves a recognizable mark on each job. It compares random and natural assignments of records to jobs, replays the null results under other submission orders, and closes the leak with a job-purged backtest. We apply it, pre-registered, to the HSBC and IBM study of fill probabilities in bond trading, which reported a large hardware-only gain. We use a public analog task and run the study's circuit on a 129-qubit chain of an IBM Heron processor. Under controlled assignment the hardware features give no gain over classical features, and the device reproduces the ideal features about as well as shot noise allows. Yet every job carries a distinct fingerprint. A circuit with no data at all predicts fills well above chance when records are batched by outcome and the same job sits on both sides of the train/test split. Removing that overlap removes the effect. The protocol costs under an hour of processor time and is designed for any hardware feature or kernel pipeline on tabular data.
The paper asks whether gains from quantum-hardware features in tabular machine learning can arise from job-dependent device drift rather than input-dependent information. Motivated by HSBC/IBM’s reported bond-fill prediction gains, it proposes five checks: interleaved data-independent null circuits, job-identification tests, randomized versus natural record assignment, replay of null outputs under alternative submission orders, and backtests excluding training records that share hardware jobs with test records.
The experiment uses 1,000 public Binance futures events, 216 classical features, and a 129-qubit Heisenberg feature circuit on IBM Heron, with 3,072 CZ gates and 1,024 shots per measurement basis. Under randomized assignment, hardware features achieve AUC 0.570 versus 0.583 classically; the paired difference is −0.013-0.013−0.013, with 95% interval [−0.075,0.047][-0.075,0.047][−0.075,0.047]. Natural chronological assignment and null circuits show no gain. Hardware features retain approximately 62% of ideal variation, with hardware–ideal correlation 0.39 versus a shot-noise ceiling of 0.42.
Null outputs identify hardware jobs perfectly despite small per-feature offsets. Reassigning them to outcome-sorted batches yields AUC 0.778, falling to 0.514 after job purging. This demonstrates a sufficient leakage mechanism, not its occurrence in HSBC’s private pipeline.
Limitations include one task, circuit family and device; an analog rather than the original dataset; fewer events and shots; and narrower model searches. The analysis plan was internally frozen before execution but not externally timestamped until publication; two procedural deviations are disclosed.
Abstract Claims of quantum advantage in machine learning often rest on classical comparators that lack the same features, on simulation alone, and on unreported hardware cost. QBioBench is a benchmark of quantum machine learning on peripheral biosignals that holds quantum and classical models to the same features and reports calibration and hardware cost. It comprises three clinical tasks, 12-lead ECG diagnosis (PTB-XL), single-lead apnea detection (Apnea-ECG), and wearable stress detection, each reduced to six to eight shared dimensions. A factorial grid of projected and fidelity quantum kernels and variational classifiers is screened in noisy simulation, and the promoted configurations are evaluated in an exploratory study on an IBM Nighthawk r2 processor on the full test pools of 510 apnea minutes and 512 PTB-XL records. Every prediction is recovered from the device records, intervals resample recordings or patients, and classical baselines are trained on the same units and tested on the same executed inputs. No quantum model reaches its matched support vector machine in ROC-AUC on either primary task, and none is separably better in balanced accuracy. The angle-encoded fidelity and projected kernels reach ROC-AUC 0.697 and 0.693 on apnea, paired differences of − 0.127 and − 0.119 to the support vector machine, and both are classical by construction, since the entangling layer of the encoding cancels from the fidelity kernel and leaves closed-form local expectations in the projected kernel. A variational classifier comes closest, reaching 0.797 on apnea (difference − 0.012 , 95% interval [ − 0.052 , + 0.027 ] ), and falls to chance without its two-qubit gates. Test sets of the size that circuit budgets favor are unreliable, as random 80-minute subsets of the apnea pool give the fidelity kernel a central 95% range of ROC-AUC from 0.589 to 0.797. Readout mitigation changed ROC-AUC by at most 0.015.
H. Billah and M.M.H. Sarker contributed equally to this work. Interpreting a fixed quantum circuit's output as evidence of a hardware effect requires ruling out two things usually conflated with it: finite-sample fluctuation, and structure already present in the circuit's own noiseless output. Less commonly checked is a third: whether the reference circuit compared against is the one actually executed, once compiler-level qubit routing is accounted for. We execute a fixed 35-qubit, 243-gate diagnostic circuit on IBM Heron-family hardware (three runs, two backends) and show this third check is essential: the routed circuit submitted to hardware has different noiseless predictions than the logical circuit intended, for several qubits. Against the correct, routed-circuit reference, the aggregate deviation is significant in two of three runs, and four registers (0, 9, 14, 27) show a significant output-probability deviation in every run — though we distinguish a high-confidence subset, {0, 9, 27}, with tightly time-matched calibration, from qubit 14, included only on an exploratory basis given its calibration was retrieved roughly two weeks post-execution. Same-backend replicates correlate more strongly by the Pearson measure, though a rank-based (Spearman) test shows this gap does not survive at the level of register ordering, indicating substantial leverage from a small number of registers rather than a broadly robust pattern; these three executions also share a byte-identical payload and are not independent replications in the strictest sense. The mechanism is only partially resolved: independent single-qubit readout error and raw gate count are ruled out as complete explanations for most of these registers, but the simplest version of the leading hypothesis for the single most-affected register does not reproduce the observed cross-backend pattern even with live, backend-specific timing data. A second, structurally different circuit validated only in simulation calibrates the statistical procedure's behavior under one synthetic noise model; it does not itself establish generality to real hardware, and the specific register set found here should not be expected to generalize beyond this study. Note on scope: this is a methodology and case-study contribution centered on executed-circuit references for fixed-circuit diagnostics, not a characterization of IBM Heron hardware in general or a randomized-benchmarking experiment in the formal sense. Supporting data, the routed OpenQASM circuits, raw measurement counts, and analysis code for this study are available on request from the corresponding author. Affiliation: Sonicium Quantum Lab Ltd., Dhaka, Bangladesh.
This project pre-registers and reports a blinded, pre-registered validation of HilbertBench, a non-intrusive diagnostic framework for quantum machine learning (QML). HilbertBench records quantum-circuit executions into append-only, cryptographically sealed traces and computes mechanism-level diagnostics — barren plateaus, shot noise, expressibility, optimization convergence, circuit structure, and hardware noise — offline, without perturbing the experiment under test. The instrument is open-source and frozen at version 1.0.0 (Zenodo DOI: 10.5281/zenodo.21009245). Purpose. We test a single question: can an analyst with no knowledge of how a QML run was produced correctly identify why it failed — barren plateau, shot starvation, noise domination, or none — using only the recorded trace and the tool's built-in analyzers? To our knowledge this is the first blinded, pre-registered validation of a QML diagnostic, modeled on the methodology of clinical trials. Design. Researcher A generates a labeled corpus of runs with planted failure modes (each label known by construction), publishes a SHA-256 cryptographic commitment of the answer key, and — only after this pre-registration is timestamped — hands the blinded runs to an independent diagnostician, Researcher B, who has not seen the corpus design. The corpus has two strata: a simulated set with clean, isolated ground truth (the primary analysis) and a real-hardware subset on a single IBM device (real-device credibility), diagnosed with primary plus optional secondary labels. Analyzer thresholds are frozen at library defaults on a disjoint development corpus before any test data is generated. Expected outcomes. We report diagnosis accuracy against the 25% four-class chance baseline with 95% Wilson confidence intervals, per-class precision/recall, and a full confusion matrix — whatever the result. We additionally pre-register a hardware prediction: on real devices, barren plateaus and noise domination are physically entangled (the circuit depth that induces an intrinsic plateau also collapses fidelity), which the confusion matrix is expected to reveal. Supporting analyses recover the McClean (2018) barren-plateau scaling exponent and validate calibration-based fidelity prediction against real hardware. All data, code, seeds, and the answer key are archived for full reproducibility.
Quantum machine learning on real noisy intermediate-scale quantum (NISQ) hardware has remained largely confined to binary or few-class tasks, limited by the cost of on-hardware training and the underuse of large devices at inference. We present a unified framework that classifies ten-class MNIST end-to-end on a 127127127-qubit IBM Eagle processor, with three central contributions. First, a two-phase protocol decouples a gradient-based classical optimization of the encoder and readout from a gradient-free optimization of the quantum parameters, removing the parameter-shift gradient cost that makes on-hardware training impractical. Second, we introduce Quantum Multi-Programming to a trained quantum classifier for the first time, packing multiple circuit copies onto one device to deliver parallel inference at no mean-accuracy cost while cutting quantum-processor job submissions proportionally. Third, a controlled comparison shows that on-hardware fine-tuning yields no measurable accuracy gain, motivating a practical NISQ workflow: train on a classical simulator and reserve the hardware for inference only. Benchmarked against a matched-capacity classical network, the quantum module shows no per-parameter accuracy advantage at this scale; we therefore frame the work as a feasibility-and-workflow demonstration for multi-class quantum image classification on current hardware.
Eight verified quantum computing jobs executed on IBM Quantum hardware (ibm_fez Heron R2, 156 qubits; ibm_torino Heron R1, 133 qubits) between January 27 and March 15, 2026. User ID: IBMid-692001DJRD. Experiments include: 1. Bell State Entanglement — 96.3% fidelity on ibm_fez Heron R2 (Concurrence C = 0.926, Tangle T = 0.858, 1,000 shots). Cross-platform benchmark: Heron R2 vs Heron R1 (+8.3 pp fidelity advantage, noise ratio 2.43×). 2. Reproducibility Test — Two independent runs of identical circuit (χ² = 2.70, p = 0.44, df = 3). H₀ not rejected: statistically indistinguishable results at 95% confidence. 3. BB84 Quantum Key Distribution — Full Alice/Eve/Bob protocol implementation. Alice baseline error 0.60% → Bob QBER 49.0% under eavesdropping (82× degradation). Experimental demonstration of the quantum no-cloning theorem. Control group design isolates eavesdropper signal from hardware noise baseline. 4. Variational Quantum Circuit (VQC) — 2-qubit circuit, 10 trained parameters with tied weights (θ₃ = θ₄), 8 CZ gates in 4 entangling layers. 4-qubit ansatz: Shannon entropy 3.885/4.000 bits (97.1%), ground-state bias confirmed (χ² = 300.94, p ≈ 0). 5. Quantum Random Number Generation (QRNG) — 8-bit outputs, 10/10 unique values per shot (range 16–254). Total: 39,010 quantum measurements across 8 jobs and 10 circuits. QPU time: 4.8 seconds. Job completion rate: 100%. All results decoded from raw IBM SamplerV2 BitArray binary archives (zlib + base64 + NumPy .npy pipeline). No simulations. Statistical validation applied throughout (Wilson 95% CIs, chi-squared tests). Stack: Qiskit Runtime SamplerV2 · QPY · OpenQASM 2.0 · Python · NumPy · SciPy Repository: https://github.com/dinohatibovicWhitepaper: https://dinohatibovic.github.io (Doc QAI-WP-2026-01-28-V4)
We present an approach for a deep-learning compiler of quantum circuits, designed to reduce the output noise of circuits run on a specific device. We train a convolutional neural network on experimental data from a quantum device to learn a hardware-specific noise model. A compiler then uses the trained network as a noise predictor and inserts sequences of gates in circuits so as to minimize expected noise. We tested this approach on the IBM 5-qubit devices and observed a reduction in output noise of 12.3% (95% CI [11.5%, 13.0%]) compared to the circuits obtained by the Qiskit compiler. Moreover, the trained noise model is hardware-specific: applying a noise model trained on one device to another device yields a noise reduction of only 5.2% (95% CI [4.9%, 5.6%]). These results suggest that device-specific compilers using machine learning may yield higher fidelity operations and provide insights for the design of noise models.