We present an approach for a deep-learning compiler of quantum circuits, designed to reduce the output noise of circuits run on a specific device. We train a convolutional neural network on experimental data from a quantum device to learn a hardware-specific noise model. A compiler then uses the trained network as a noise predictor and inserts sequences of gates in circuits so as to minimize expected noise. We tested this approach on the IBM 5-qubit devices and observed a reduction in output noise of 12.3% (95% CI [11.5%, 13.0%]) compared to the circuits obtained by the Qiskit compiler. Moreover, the trained noise model is hardware-specific: applying a noise model trained on one device to another device yields a noise reduction of only 5.2% (95% CI [4.9%, 5.6%]). These results suggest that device-specific compilers using machine learning may yield higher fidelity operations and provide insights for the design of noise models.
We present an approach for a deep-learning compiler of quantum circuits, designed to reduce the output noise of circuits run on a specific device. We train a convolutional neural network on experimental data from a quantum device to learn a hardware-specific noise model. A compiler then uses the trained network as a noise predictor and inserts sequences of gates in circuits so as to minimize expected noise. We tested this approach on the IBM 5-qubit devices and observed a reduction in output noise of 12.3% (95% CI [11.5%, 13.0%]) compared to the circuits obtained by the Qiskit compiler. Moreover, the trained noise model is hardware-specific: applying a noise model trained on one device to another device yields a noise reduction of only 5.2% (95% CI [4.9%, 5.6%]). These results suggest that device-specific compilers using machine learning may yield higher fidelity operations and provide insights for the design of noise models.
Maximizing the computational utility of near-term quantum processors requires predictive noise models that inform robust, noise-aware compilation and error mitigation. Conventional models often fail to capture the complex error dynamics of real hardware or require prohibitive characterization overhead. We introduce a data-efficient framework that first constructs a physically motivated, parameterized noise model, and subsequently employs machine-learning-driven Bayesian optimization to identify its parameters. Our approach circumvents costly characterization protocols by estimating algorithm- and hardware-specific error parameters directly from readily available experimental data derived from existing application and benchmark circuit executions. The generality and robustness of the framework are demonstrated across diverse algorithms and superconducting devices, yielding high-fidelity predictions by estimating an independent parameter set tailored to each specific algorithm-hardware context. Crucially, we show that a model calibrated exclusively on small-scale circuits accurately predicts the behavior of larger validation circuits. Our data-efficient approach achieves up to a 65% improvement in model fidelity quantified by the Hellinger distance between predicted and experimental circuit output distributions, compared to standard noise models derived from device properties. This work establishes a practical paradigm for application-aware noise characterization, enabling compilation and error-mitigation strategies tailored to the specific interplay between quantum algorithms and device-specific noise dynamics.
We present a systematic investigation of deep learning methods applied to quantum error mitigation of noisy output probability distributions from measured quantum circuits. We compare different architectures, from fully connected neural networks to transformers, and we test different design/training modalities, identifying sequence-to-sequence, attention-based models as the most effective on our datasets. These models consistently produce mitigated distributions that are closer to the ideal outputs when tested on both simulated and real device data obtained from IBM superconducting quantum processing units (QPU) up to five qubits. Across several different circuit depths, our approach outperforms other baseline error mitigation techniques. We perform a series of ablation studies to examine: how different input features (circuit, device properties, noisy output statistics) affect performance; cross-dataset generalization across circuit families; and transfer learning to a different IBM QPU. We observe that generalization performance across similar devices with the same architecture works effectively, without needing to fully retrain models.
Hybridizing machine learning (ML) with quantum computing has become an attractive strategy to increase computational power on Noisy Intermediate Scale Quantum (NISQ) devices. Although these can be potentially quantum advantage devices, their qubit numbers and noise are bounded and there are challenges when it comes to practical quantum circuit realization. This work concentrates on the creation of optimized quantum circuits via ML-based strategies, to enhance the performance of the circuits, to reduce the error rate and to accommodate the particular noise profile of the hardware of NISQ devices. The resulting suboptimal mappings with little or no consideration of noise and hardware topology in traditional quantum compilers can ruin the fidelity of quantum algorithm. Leveraging machine learning, and specifically reinforcement and supervised learning methods, our method learns to optimize compilation strategy for specific quantum hardware architecture. The paper proposes a framework that uses machine learning models to predict qubit mappings, gate decompositions, and transpilation paths that minimize gate depth and error accumulation. We also investigate transfer learning methods for propagating the learned compilation strategies to novel NISQ machines. Such methods are empirically validated on both simulated and real quantum hardware backends, providing evidence of circuit depth, execution time and error reductions. The results show that ML-assisted compilation can achieve better success probabilities for benchmark quantum algorithms like VQE and QAOA than conventional compilers. Furthermore, the work examines the interpretability of ML models providing hardware-aware optimization recommendations and understanding the noise patterns and methods of error correction. Our work highlights the key role of ML for transferring between theoretical quantum algorithms and their practical NISQ implementations. This integration boosts the immediate applicability of existing quantum devices and provides a basis for adaptive and scalable likelihood-based compilation for the era of fault-tolerant quantum computation. Our results motivate further investigation of hybrid classical-quantum workflows, in which ML iteratively improves compilation in accordance with changing hardware noise and capabilities. By improving quantum circuit compilation onNISQ computers, this work is taking steps toward the realization of quantum advantage in application scenarios such as optimization, cryptography, and quantum simulation without needing to wait for fully fault-tolerant large-scale quantum computers.
Abstract Predicting the output of quantum circuits is a hard computational task that plays a pivotal role in the development of universal quantum computers. Here we investigate the supervised learning of output expectation values of random quantum circuits. Deep convolutional neural networks (CNNs) are trained to predict single-qubit and two-qubit expectation values using databases of classically simulated circuits. These circuits are built using either a universal gate set or a continuous set of rotations plus an entangling gate, and they are represented via properly designed encodings of these gates. The prediction accuracy for previously unseen circuits is analyzed, also making comparisons with small-scale quantum computers available from the free IBM Quantum program. The CNNs often outperform these quantum devices, depending on the circuit depth, on the network depth, and on the training set size. Notably, our CNNs are designed to be scalable. This allows us exploiting transfer learning and performing extrapolations to circuits larger than those included in the training set. These CNNs also demonstrate remarkable resilience against noise, namely, they remain accurate even when trained on (simulated) expectation values averaged over very few measurements.
In the noisy intermediate-scale quantum (NISQ) regime, quantum devices contain hardware-specific noise sources which restrict device-invariant error mitigation strategies. We explore transfer learning approaches to apply noise models learned on one quantum device to a different device with the help of a small amount of data. We create a real-hardware dataset from two IBM quantum devices, ibm_fez (source) and ibm_marrakesh (target), comprising 170 noisy and ideal circuit output distributions, with device calibration features added. We train a residual neural network on the source device to map noisy to ideal outcomes. The zero-shot transfer test shows a KL divergence of 1.6706 (up from 0.3014), establishing device specificity. With K = 20 fine-tuning samples, KL drops to 1.1924 (28.6% improvement over zero-shot), recovering 34.9% of the gap between zero-shot and in-domain KL. Ablation studies reveal that the major cause of mismatches across devices is CX gate error, followed by readout error. The results show quantum noise can be learned and fine-tuned with minimal samples, and provide a plausible approach to cross-device quantum error mitigation.
A central aspect for operating future quantum computers is quantum circuit optimization, i.e., the search for efficient realizations of quantum algorithms given the device capabilities. In recent years, powerful approaches have been developed which focus on optimizing the high-level circuit structure. However, these approaches do not consider and thus cannot optimize for the hardware details of the quantum architecture, which is especially important for near-term devices. To address this point, we present an approach to quantum circuit optimization based on reinforcement learning. We demonstrate how an agent, realized by a deep convolutional neural network, can autonomously learn generic strategies to optimize arbitrary circuits on a specific architecture, where the optimization target can be chosen freely by the user. We demonstrate the feasibility of this approach by training agents on 12-qubit random circuits, where we find on average a depth reduction by 27% and a gate count reduction by 15%. We examine the extrapolation to larger circuits than used for training, and envision how this approach can be utilized for near-term quantum devices.