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A Fidelity-Aware Framework for Joint Circuit Knitting and Error Mitigation

Matteo Mendula, Deborah Volpe, Fabrizio Riente, Giovanna Turvani, Carla Fabiana Chiasserini

Published Jan 1, 2026• 0 citations
OpenAlex

Abstract

Executing quantum circuits on current quantum Best Cut Identification devices is fundamentally limited by noise, decoherence, and hardware constraints. Circuit Knitting (CK) techniques enable the execution of larger circuits by decomposing them into smaller sub-circuits, at the cost of reconstruction overhead. At the same time, Quantum Error Mitigation (QEM) methods improve fidelity but introduce additional complexity. In this work, we propose a fidelity-aware framework that jointly optimizes circuit partitioning and error mitigation to maximize end-to-end execution fidelity. We introduce a unified model that captures the trade-off between sub-circuit operational fidelity, reconstruction penalties induced by cuts, and the impact of error mitigation. Based on this model, we formulate the cut placement problem as an optimization task and solve it to identify fidelity-optimal partitioning strategies accounting for error mitigation and under realistic hardware constraints. Notably, our framework integrates calibration-driven noise models and supports practical fidelity estimation using backend-specific parameters. We validate the proposed method on both noisy simulators (IBM Fake Backends) and real quantum hardware (IQM Lagrange), proving consistent improvements in execution fidelity with gains of up to 40% over standard circuit execution.

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Executing quantum circuits on current quantum Best Cut Identification devices is fundamentally limited by noise, decoherence, and hardware constraints. Circuit Knitting (CK) techniques enable the execution of larger circuits by decomposing them into smaller sub-circuits, at the cost of reconstruction overhead. At the same time, Quantum Error Mitigation (QEM) methods improve fidelity but introduce additional complexity. In this work, we propose a fidelity-aware framework that jointly optimizes circuit partitioning and error mitigation to maximize end-to-end execution fidelity. We introduce a unified model that captures the trade-off between sub-circuit operational fidelity, reconstruction penalties induced by cuts, and the impact of error mitigation. Based on this model, we formulate the cut placement problem as an optimization task and solve it to identify fidelity-optimal partitioning strategies accounting for error mitigation and under realistic hardware constraints. Notably, our framework integrates calibration-driven noise models and supports practical fidelity estimation using backend-specific parameters. We validate the proposed method on both noisy simulators (IBM Fake Backends) and real quantum hardware (IQM Lagrange), proving consistent improvements in execution fidelity with gains of up to 40% over standard circuit execution.
Executing quantum circuits on NISQ devices poses challenges due to noise, decoherence, and limited qubit counts. Circuit Knitting (CK) allows solving these issues by breaking down large circuits into smaller sub-circuits. However, the subsequent reconstruction adds sampling and processing time. Quantum Error Mitigation (QEM) can enhance output quality, but it also raises execution costs. To address the above issues, we introduce MOSAIQ, a cost-aware framework optimizing both circuit partitioning and error mitigation for reliable NISQ execution. MOSAIQ uses calibration-driven noise estimation, mitigation-aware fidelity modeling, and cut-dependent recon- struction costs to choose partitioning strategies that balance end- to-end fidelity with practical feasibility. We define the problem as an optimization task and test the MOSAIQ on noisy simulators and actual quantum HW. Results indicate that MOSAIQ prevents overly aggressive partitioning and improves the balance between fidelity, sampling overhead, and execution time.
Abstract Suppressing errors is one of the central challenges in achieving reliable quantum computation on near-term hardware. While much attention has been paid to error correction and mitigation, we identify quantum circuit structure itself as a powerful lever for proactive error suppression. In this work, we present a unified and hardware-adaptive framework for noise-aware quantum circuit design, in which circuit topology and parameters are co-optimized from the ground up based on the noise profile of the target backend. Our framework supports a wide range of quantum tasks-including circuit compilation, quantum state preparation, and unitary approximation-under a consistent optimization paradigm. Extensive experiments on five IBM backends confirm the effectiveness of our method, showing significant fidelity gains across all tasks under realistic noise. These results demonstrate that noise suppression through structure-aware design offers a powerful and generalizable strategy for enhancing circuit performance on NISQ hardware. Our framework bridges low-level hardware constraints with high-level circuit synthesis, paving the way for more robust and efficient quantum programming in the presence of noise.
Noise in contemporary quantum hardware is highly non-uniform across qubits and couplers, giving rise to localized low-noise "islands" within otherwise noisy device topologies. As quantum workloads scale, executions are increasingly forced to traverse high-noise regions, degrading algorithmic fidelity. Circuit cutting provides a route to circumvent such regions by decomposing large circuits into smaller subcircuits, but its practicality is limited by exponential sampling overhead and the lack of systematic guidance on how cut strategies should align with heterogeneous hardware noise. In this work, we present a hardware-noise-aware circuit cutting framework that explicitly exploits the spatial non-uniformity of noise in quantum devices. Rather than proposing a new cut-finding algorithm, we formalize the problem of device-constraint selection under realistic hardware noise and show that this choice critically determines both execution overhead and effective noise. Using a unified gate- and wire-cutting formulation, we demonstrate that small, hardware-informed relaxations in the device constraint yield exponential reductions in execution overhead while preserving alignment with low-noise hardware regions. Across representative workloads, our method achieves an average reduction in the number of circuit executions ranging from 5-54x for 20-qubit circuits, and enables tractable circuit cutting for 50-qubit circuits and application-level benchmarks where conventional strategies incur prohibitive overhead. These results establish noise-aware device-constraint selection as a necessary ingredient for making circuit cutting resource-efficient and practically deployable on contemporary quantum hardware.
Circuit knitting emerges as a promising technique to overcome the limitation of the few physical qubits in near-term quantum hardware by cutting large quantum circuits into smaller subcircuits. Recent research in this area has been primarily oriented towards reducing subcircuit sampling overhead. Unfortunately, these works neglect hardware information during circuit cutting, thus posing significant challenges to the follow on stages. In fact, direct compilation and execution of these partitioned subcircuits yields low-fidelity results, highlighting the need for a more holistic optimization strategy.
We experimentally study error mitigation and finite-shot sampling on superconducting quantum hardware under a constrained execution budget. The study combines calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation on an IBM Quantum processor. Experiments are organized across ideal simulation, noise-model simulation, and physical-device execution to separate sampling uncertainty from device-induced error. We investigate how mitigation performance changes with circuit depth, effective noise scale, qubit connectivity, and measurement budget, and quantify accuracy using expectation-value error, mean-squared error, statistical uncertainty, and mitigation gain. A fixed hardware-execution budget is used to evaluate shot allocation strategies and repeated measurements without relying on unlimited sampling. The resulting analysis provides a hardware-aware characterization of when mitigation improves expectation-value estimation and when finite-shot fluctuations offset the benefit of additional mitigation overhead. The implementation uses contemporary Qiskit and IBM Quantum Runtime workflows and is designed to provide reproducible experimental evidence for error-mitigation studies on current quantum processors.
Current quantum computers do not yet have the required qubit resources to meet the demands of most practical quantum algorithms. To circumvent this constraint, the practice of dividing these algorithms into parts through quantum circuit cutting has been explored. Many of these works either show exponential scaling or are far from optimal solutions. In this paper, MosaiQC is presented as a novel framework to improve upon existing circuit cutting frameworks. A hybrid warmstart with refinement optimization is used to find cutting solutions, allowing the combination of both wire and gate cuts. Additionally, MosaiQC enables hardware partitions of mixed sizes. Furthermore, the refinement stage incorporates a fast approximate quadratic assignment solver to better place hardware partitions, demonstrating a mean local fidelity improvement of 19.56%±6.17%19.56 \% \pm 6.17\%19.56%±6.17% over the baseline algorithm. In runtime and sampling overhead costs, improvements of 2.88×2.88 \times2.88× and an average of 16.84%16.84\%16.84% cut reduction (resulting in an average 5.83⋅1011×5.83 \cdot 10^{11} \times5.83⋅1011× overhead reduction) are observed. MosaiQC demonstrates a superior trade-off for run speed and solution quality, while adding fundamental features excluded by most competitors. With this, MosaiQC demonstrates that scalable heuristic optimization can substantially reduce the computational overhead of circuit-cut placement for increasingly large quantum circuits.