Current quantum computers do not yet have the required qubit resources to meet the demands of most practical quantum algorithms. To circumvent this constraint, the practice of dividing these algorithms into parts through quantum circuit cutting has been explored. Many of these works either show exponential scaling or are far from optimal solutions. In this paper, MosaiQC is presented as a novel framework to improve upon existing circuit cutting frameworks. A hybrid warmstart with refinement optimization is used to find cutting solutions, allowing the combination of both wire and gate cuts. Additionally, MosaiQC enables hardware partitions of mixed sizes. Furthermore, the refinement stage incorporates a fast approximate quadratic assignment solver to better place hardware partitions, demonstrating a mean local fidelity improvement of $19.56 \% \pm 6.17\%$ over the baseline algorithm. In runtime and sampling overhead costs, improvements of $2.88 \times$ and an average of $16.84\%$ cut reduction (resulting in an average $5.83 \cdot 10^{11} \times$ overhead reduction) are observed. MosaiQC demonstrates a superior trade-off for run speed and solution quality, while adding fundamental features excluded by most competitors. With this, MosaiQC demonstrates that scalable heuristic optimization can substantially reduce the computational overhead of circuit-cut placement for increasingly large quantum circuits.
Current quantum computers do not yet have the required qubit resources to meet the demands of most practical quantum algorithms. To circumvent this constraint, the practice of dividing these algorithms into parts through quantum circuit cutting has been explored. Many of these works either show exponential scaling or are far from optimal solutions. In this paper, MosaiQC is presented as a novel framework to improve upon existing circuit cutting frameworks. A hybrid warmstart with refinement optimization is used to find cutting solutions, allowing the combination of both wire and gate cuts. Additionally, MosaiQC enables hardware partitions of mixed sizes. Furthermore, the refinement stage incorporates a fast approximate quadratic assignment solver to better place hardware partitions, demonstrating a mean local fidelity improvement of 19.56%±6.17% over the baseline algorithm. In runtime and sampling overhead costs, improvements of 2.88× and an average of 16.84% cut reduction (resulting in an average 5.83⋅1011× overhead reduction) are observed. MosaiQC demonstrates a superior trade-off for run speed and solution quality, while adding fundamental features excluded by most competitors. With this, MosaiQC demonstrates that scalable heuristic optimization can substantially reduce the computational overhead of circuit-cut placement for increasingly large quantum circuits.
Noise in contemporary quantum hardware is highly non-uniform across qubits and couplers, giving rise to localized low-noise "islands" within otherwise noisy device topologies. As quantum workloads scale, executions are increasingly forced to traverse high-noise regions, degrading algorithmic fidelity. Circuit cutting provides a route to circumvent such regions by decomposing large circuits into smaller subcircuits, but its practicality is limited by exponential sampling overhead and the lack of systematic guidance on how cut strategies should align with heterogeneous hardware noise. In this work, we present a hardware-noise-aware circuit cutting framework that explicitly exploits the spatial non-uniformity of noise in quantum devices. Rather than proposing a new cut-finding algorithm, we formalize the problem of device-constraint selection under realistic hardware noise and show that this choice critically determines both execution overhead and effective noise. Using a unified gate- and wire-cutting formulation, we demonstrate that small, hardware-informed relaxations in the device constraint yield exponential reductions in execution overhead while preserving alignment with low-noise hardware regions. Across representative workloads, our method achieves an average reduction in the number of circuit executions ranging from 5-54x for 20-qubit circuits, and enables tractable circuit cutting for 50-qubit circuits and application-level benchmarks where conventional strategies incur prohibitive overhead. These results establish noise-aware device-constraint selection as a necessary ingredient for making circuit cutting resource-efficient and practically deployable on contemporary quantum hardware.
Quantum circuit cutting enables the execution of large circuits on devices with a limited number of qubits by partitioning circuits into independent subcircuits. However, this introduces a sampling overhead, which grows exponentially with the number of cuts, rendering the choice of cut placements critical for practical circuit cutting. Determining optimal cut placements remains computationally challenging, particularly as circuits grow in size. Additionally, existing circuit cutting approaches typically treat gate and wire cuts independently. Those combining both cutting approaches, however, do not take advantage of joint cutting, i.e., identifying common gate groups and cutting them jointly for a reduced overhead. This work presents a unified framework that combines gate and wire cutting within a single partitioning strategy, enabling more efficient circuit decompositions. Moreover, our approach incorporates joint cutting via a novel gate grouping technique, further reducing sampling overhead. By formulating the cut placement problem as a scalable graph partitioning task, our method efficiently identifies near-optimal cut placements for large circuits, also providing diagnostic feedback on whether circuits are suitable for cutting.
A limited number of qubits, high error rates, and limited qubit connectivity are major challenges for effective near-term quantum computations. Quantum circuit partitioning divides a quantum computation into classical postprocessing steps and a set of smaller-scale quantum computations that individually require fewer qubits, lower qubit connectivity, and typically incur less error. However, as partitioning generally increases the duration of a quantum computation exponentially in the required partitioning effort, it is crucial to select optimal partitioning points, so-called cuts, and to use optimal cut realizations. In this work, we develop the first optimal partitioning method relying on quantum circuit knitting for optimal cut realizations and an optimal selection of wire cuts and gate cuts that trades off ancilla qubit insertions for a decrease in quantum computing time. Using this combination, the developed method demonstrates a reduction in quantum computing runtime by 41% on average compared to previous quantum circuit partitioning methods. Furthermore, the qubit requirement of the evaluated quantum circuits was reduced by 40% on average for a runtime budget of one hour and a sampling frequency of 1 kHz. These results highlight the optimality gap of previous quantum circuit partitioning methods and the possible extension in the computational reach of near-term quantum computers.
Executing quantum circuits on current quantum Best Cut Identification devices is fundamentally limited by noise, decoherence, and hardware constraints. Circuit Knitting (CK) techniques enable the execution of larger circuits by decomposing them into smaller sub-circuits, at the cost of reconstruction overhead. At the same time, Quantum Error Mitigation (QEM) methods improve fidelity but introduce additional complexity. In this work, we propose a fidelity-aware framework that jointly optimizes circuit partitioning and error mitigation to maximize end-to-end execution fidelity. We introduce a unified model that captures the trade-off between sub-circuit operational fidelity, reconstruction penalties induced by cuts, and the impact of error mitigation. Based on this model, we formulate the cut placement problem as an optimization task and solve it to identify fidelity-optimal partitioning strategies accounting for error mitigation and under realistic hardware constraints. Notably, our framework integrates calibration-driven noise models and supports practical fidelity estimation using backend-specific parameters. We validate the proposed method on both noisy simulators (IBM Fake Backends) and real quantum hardware (IQM Lagrange), proving consistent improvements in execution fidelity with gains of up to 40% over standard circuit execution.
Simulating molecular systems on quantum processors has the potential to surpass classical methods in computational resource efficiency. The limited qubit connectivity, small processor size, and short coherence times of near-term quantum hardware constrain the applicability of quantum algorithms like QPE and VQE. Quantum circuit cutting mitigates these constraints by partitioning large circuits into smaller subcircuits, enabling execution on resource-limited devices. However, finding optimal circuit partitions remains a significant challenge, affecting both computational efficiency and accuracy. To address these limitations, in this article, we propose CutQAS, a novel framework that integrates quantum circuit cutting with quantum architecture search (QAS) to enhance quantum chemistry simulations. Our framework employs a multi-step reinforcement learning (RL) agent to optimize circuit configurations. First, an RL agent explores all possible topologies to identify an optimal circuit structure. Subsequently, a second RL agent refines the selected topology by determining optimal circuit cuts, ensuring efficient execution on constrained hardware. Through numerical simulations, we demonstrate the effectiveness of our method in improving simulation accuracy and resource efficiency. This approach presents a scalable solution for quantum chemistry applications, offering a systematic pathway to overcoming hardware constraints in near-term quantum computing.
The current noisy intermediate-scale quantum (NISQ) era is characterized by substantial errors and noise, which limit the practical feasibility of deep, many-qubit circuits. To address these constraints, quantum circuit cutting has emerged as a promising tool. Recently, there has been significant research on methods for performing such cutting effectively. In this work, the duality between quantum circuits and classical graphs - specifically, directed acyclic graphs (dags) - is leveraged to analyze the complexity of finding an optimal circuit-cutting configuration that minimizes the number of cuts. After developing a rigorous graph-theoretic framework, the complexity of identifying cut locations that partition a given quantum circuit into smaller fragments is characterized. The corresponding graph-combinatorial task is then defined, and the resulting partition problem is shown to be NP-complete. Furthermore, even a simplified version of the problem, restricted to circuits composed only of one- and two-qubit gates, is shown to be NP-complete. Finally, based on these constraints, an algorithm grounded in satisfiability modulo theories (SMT) is proposed to find optimal cuts when the number of qubits per partition is bounded. This work therefore provides a complexity-theoretic characterization of cut placement and a practical solver for bounded-size decompositions.