Abstract Suppressing errors is one of the central challenges in achieving reliable quantum computation on near-term hardware. While much attention has been paid to error correction and mitigation, we identify quantum circuit structure itself as a powerful lever for proactive error suppression. In this work, we present a unified and hardware-adaptive framework for noise-aware quantum circuit design, in which circuit topology and parameters are co-optimized from the ground up based on the noise profile of the target backend. Our framework supports a wide range of quantum tasks-including circuit compilation, quantum state preparation, and unitary approximation-under a consistent optimization paradigm. Extensive experiments on five IBM backends confirm the effectiveness of our method, showing significant fidelity gains across all tasks under realistic noise. These results demonstrate that noise suppression through structure-aware design offers a powerful and generalizable strategy for enhancing circuit performance on NISQ hardware. Our framework bridges low-level hardware constraints with high-level circuit synthesis, paving the way for more robust and efficient quantum programming in the presence of noise.
Abstract Suppressing errors is one of the central challenges in achieving reliable quantum computation on near-term hardware. While much attention has been paid to error correction and mitigation, we identify quantum circuit structure itself as a powerful lever for proactive error suppression. In this work, we present a unified and hardware-adaptive framework for noise-aware quantum circuit design, in which circuit topology and parameters are co-optimized from the ground up based on the noise profile of the target backend. Our framework supports a wide range of quantum tasks-including circuit compilation, quantum state preparation, and unitary approximation-under a consistent optimization paradigm. Extensive experiments on five IBM backends confirm the effectiveness of our method, showing significant fidelity gains across all tasks under realistic noise. These results demonstrate that noise suppression through structure-aware design offers a powerful and generalizable strategy for enhancing circuit performance on NISQ hardware. Our framework bridges low-level hardware constraints with high-level circuit synthesis, paving the way for more robust and efficient quantum programming in the presence of noise.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
Abstract Accurately characterizing and mitigating the impact of noise is essential for improving the fidelity of quantum simulations on Noisy Intermediate-Scale Quantum (NISQ) devices. In this work, we introduce a circuit-structure-preserving error-mitigation framework designed for parameterized quantum circuits. Unlike conventional approaches that alter circuit topology or require heavy post-processing, our method preserves the native architecture while systematically diagnosing gate noise. This structure-preserving feature enables robust, high-fidelity simulations even in the presence of significant hardware noise, making the approach particularly effective for small-scale circuits executed at high sampling rates, such as those used in variational algorithms and quantum neural networks. To benchmark its performance, we apply the method to variational quantum simulations of a non-Hermitian ferromagnetic transverse-field Ising chain implemented on IBM Quantum processors. The mitigated results exhibit excellent agreement with exact theoretical predictions across a wide range of noise conditions. Thus, our framework provides a scalable and hardware-efficient strategy for the current hardware.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
This paper presents a novel approach to quantum circuit compilation that leverages the feedback capabilities of the Variational Quantum Eigensolver (VQE) to achieve adaptive optimization. Traditional quantum compilation methods are static, assuming a known and consistent noise profile for the target quantum hardware. However, real quantum devices exhibit significant noise variations, leading to suboptimal circuit execution. Our strategy addresses this challenge by dynamically adjusting compilation parameters based on the VQE's error estimations during runtime. The core idea is to implement a real-time optimization loop where the VQE provides error estimates for individual gate operations, and the compiler subsequently modifies the circuit topology and gate choices to minimize overall error. This adaptive compilation scheme allows the quantum circuit to 'learn' the noise characteristics of the hardware, leading to a reduction in gate count and improved fidelity. The presented framework offers a pathway towards more robust and efficient quantum computation, particularly relevant as quantum hardware matures and noise mitigation techniques become more sophisticated. We outline the key components of the system, including the VQE integration, the compilation algorithm, and a discussion of potential challenges and future research directions.
Quantum computing is entering a transitional regime between noisy intermediate-scale quantum (NISQ) processing and early fault-tolerant quantum computation (FTQC), in which increasingly capable hardware is beginning to support repeated syndrome measurements, partial error correction, and logical-qubit operations, while residual physical and logical errors remain non-negligible. In this regime, error suppression, error mitigation, and quantum error correction are increasingly better viewed as complementary layers of a unified error-reduction strategy rather than as separate approaches, with each acting at a different stage of the quantum computation to improve simulation reliability. Thus, in this review, we provide a practical and forward-looking overview of the principal hardware error sources and the corresponding error suppression and mitigation methods for reducing their impact across the current NISQ-FTQC transition. We discuss hardware-aware circuit design, coherent-error suppression, readout mitigation, noise extrapolation, classical inference, and software-supported workflows, with particular emphasis on their implementation on actual quantum processors. We further examine how error mitigation techniques can be adapted to encoded and logical-qubit settings so that they can operate alongside quantum error correction to suppress residual logical errors and improve the accuracy of computation in the early fault-tolerant regime.