Quantum computing is entering a transitional regime between noisy intermediate-scale quantum (NISQ) processing and early fault-tolerant quantum computation (FTQC), in which increasingly capable hardware is beginning to support repeated syndrome measurements, partial error correction, and logical-qubit operations, while residual physical and logical errors remain non-negligible. In this regime, error suppression, error mitigation, and quantum error correction are increasingly better viewed as complementary layers of a unified error-reduction strategy rather than as separate approaches, with each acting at a different stage of the quantum computation to improve simulation reliability. Thus, in this review, we provide a practical and forward-looking overview of the principal hardware error sources and the corresponding error suppression and mitigation methods for reducing their impact across the current NISQ-FTQC transition. We discuss hardware-aware circuit design, coherent-error suppression, readout mitigation, noise extrapolation, classical inference, and software-supported workflows, with particular emphasis on their implementation on actual quantum processors. We further examine how error mitigation techniques can be adapted to encoded and logical-qubit settings so that they can operate alongside quantum error correction to suppress residual logical errors and improve the accuracy of computation in the early fault-tolerant regime.
Quantum computing is entering a transitional regime between noisy intermediate-scale quantum (NISQ) processing and early fault-tolerant quantum computation (FTQC), in which increasingly capable hardware is beginning to support repeated syndrome measurements, partial error correction, and logical-qubit operations, while residual physical and logical errors remain non-negligible. In this regime, error suppression, error mitigation, and quantum error correction are increasingly better viewed as complementary layers of a unified error-reduction strategy rather than as separate approaches, with each acting at a different stage of the quantum computation to improve simulation reliability. Thus, in this review, we provide a practical and forward-looking overview of the principal hardware error sources and the corresponding error suppression and mitigation methods for reducing their impact across the current NISQ-FTQC transition. We discuss hardware-aware circuit design, coherent-error suppression, readout mitigation, noise extrapolation, classical inference, and software-supported workflows, with particular emphasis on their implementation on actual quantum processors. We further examine how error mitigation techniques can be adapted to encoded and logical-qubit settings so that they can operate alongside quantum error correction to suppress residual logical errors and improve the accuracy of computation in the early fault-tolerant regime.
Fault-tolerant quantum computing (FTQC) is a form of universal quantum computing that suppresses physical errors via quantum error correction (QEC). On the other hand, it is expected that the available code distance and the T-gate count will be restricted in the early years of FTQC. Meanwhile, quantum error mitigation (QEM) was recently introduced for suppressing errors in noisy intermediate-scale quantum (NISQ) devices; it improves the computation accuracy of near-term quantum algorithms with its overhead being a greater number of samples. In this work, we integrate QEC and QEM into an efficient FTQC architecture that effectively increases the code distance and T-gate count. Our scheme will dramatically alleviate the required qubit count by tens of percent at the cost of a constant multiplicative sampling overhead within 102 in a wide range of regimes from the post-NISQ era to early FTQC regime, which necessitates the order of from 104 to 1010 logical operations. While it has been widely believed that there do not exist useful applications in post-NISQ regimes due to a chasm between the NISQ and FTQC regimes such as overheads for encoding and T-gate distillations, our scheme can continuously bridge the two distinct regimes.
A long-standing challenge in quantum computing is developing technologies to overcome the inevitable noise in qubits. To enable meaningful applications in the early stages of fault-tolerant quantum computing, devising methods to suppress post-correction logical failures is becoming increasingly crucial. In this work, we propose and experimentally demonstrate the application of zero-noise extrapolation, a practical quantum error mitigation technique, to error correction circuits on superconducting processors. By amplifying the noise on physical qubits, the circuits yield outcomes that exhibit a predictable dependence on noise strength, following a polynomial function determined by the code distance. This property enables the effective application of polynomial extrapolation to mitigate logical errors. Our experiments demonstrate a universal reduction in logical errors across various quantum circuits, including fault-tolerant circuits of repetition and surface codes. We observe a favorable performance in multi-round error correction circuits, indicating that this method remains effective when the circuit depth increases. These results advance the frontier of quantum error suppression technologies, opening a practical way to achieve reliable quantum computing in the early fault-tolerant era. Quantum error mitigation refers to techniques that reduce, rather than correct, errors in quantum computing. Here the authors demonstrate zero-noise extrapolation applied to quantum error correction circuits on superconducting processors, effectively reducing logical errors and advancing early fault-tolerant quantum computing.
The recent pace of experimental progress in quantum technologies suggests we may soon reach a time when quantum devices can be applied to solve problems of practical interest. Despite this, we are still far from being able to abstract away the effects of noise on quantum computation. The reliable execution of computations on current devices remains a significant challenge. This holds true both for computation with noisy physical qubits and for computation using the limited forms of error correction available on early fault-tolerant quantum devices. In this thesis, I propose methods for improving the reliability of quantum devices, as the field transitions from the regime of noisy intermediate-scale quantum (NISQ) devices to that of early fault-tolerance. These span the topics of quantum error mitigation, quantum error correction and quantum certification. In the first instance, I propose methods for improving the performance of quantum devices affected by limited amounts of noise. Specifically, I present a method for mitigating the effects of time-dependent noise. This adapts a computational certification protocol called accreditation into a method for postselecting on weaker time-dependent noise behaviours. The method is analytically shown to lead to a provable reduction in errors for the case of depolarising noise, and demonstrated in experiments on superconducting hardware. I also present a method for mitigating the effects of photon loss in photonic quantum devices. Through a combination of analytical and numerical analysis, it is shown that there are wide regimes of photon loss for which this method outperforms postselection, the standard method of handling loss in photonic devices. Additionally, evidence is provided that the method enhances the performance of a quantum machine learning model known as a Quantum Circuit Born Machine in the presence of photon loss. Next, I introduce a framework for certifying the correctness of computations run on encoded logical qubits. This is sensitive to considerably more general forms of noise than is usually considered in quantum error correction. It can be applied to efficiently certify the correctness of quantum computations for large system sizes, beyond the capabilities of methods relying on classical simulation. In numerical experiments, the framework was applied to certify the accuracy of instantaneous quantum polynomial (IQP) circuit sampling and Trotterised Hamiltonian simulation. It can be used to efficiently assess whether quantum error mitigation may be usefully applied to a computation, to upper-bound the infidelity of the encoded logical state, and to extend the method of entropy density benchmarking to logical computation. The methods presented in this thesis contribute to the wider effort of building towards reliable quantum computation: both in the sense of reducing the effects of noise on computational output, and in the sense of certifying the correctness of computation beyond the capabilities of classical simulators. Only with reliable quantum computation can the full potential of this technology be realised.
Quantum computing promises to address problems in simulation, optimization, and chemistry, but current hardware operates in the noisy intermediate-scale (NISQ) regime where coherence limits, gate imperfections, and readout errors restrict performance. Improving calibration and mitigating errors therefore remain essential. This thesis analyzes error reduction on superconducting transmon qubits through calibration, gate analysis, and circuit-level mitigation. It compares single-qubit amplitude calibration methods and analyzes two-qubit gates based on the cross-resonance interaction, identifying differences in precision, convergence, and performance. In addition, it develops Inverted-Circuit Zero-Noise-Extrapolation (IC-ZNE) which measures effective error strength using inverted circuits. Compared to standard ZNE, IC-ZNE achieves results closer to ideal values and reduces observable errors. Overall, the presented methods improve the reliability of near-term quantum processors.
Quantum systems operate using quantum bits (qubits), which are highly sensitive to external noises and disturbances and they are easily prone to errors. In the Noisy Intermediate-Scale Quantum (NISQ) era, these errors make difficult to build reliable, fault tolerant quantum circuits for real world deployment. This work provides an overview of need for Quantum Error Correction (QEC) in NISQ devices, as qubits commonly get affected by bit-flip, phase-flip, and combined errors that degrades system performance and examines Quantum Error Correction Code (QECC) techniques usage in communication, computation, and quantum multimedia applications such as image and video transmission. In addition, a simple three-qubit repetition circuit is introduced to demonstrate an error-mitigation approach. These findings, also show how QEC improves fidelity, reduces logical errors, and improves noise tolerance. The analysis also identifies challenges and outlines the future research direction aimed at achieving efficient and scalable fault tolerant quantum circuits.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.