Circuit knitting emerges as a promising technique to overcome the limitation of the few physical qubits in near-term quantum hardware by cutting large quantum circuits into smaller subcircuits. Recent research in this area has been primarily oriented towards reducing subcircuit sampling overhead. Unfortunately, these works neglect hardware information during circuit cutting, thus posing significant challenges to the follow on stages. In fact, direct compilation and execution of these partitioned subcircuits yields low-fidelity results, highlighting the need for a more holistic optimization strategy.
Circuit knitting emerges as a promising technique to overcome the limitation of the few physical qubits in near-term quantum hardware by cutting large quantum circuits into smaller subcircuits. Recent research in this area has been primarily oriented towards reducing subcircuit sampling overhead. Unfortunately, these works neglect hardware information during circuit cutting, thus posing significant challenges to the follow on stages. In fact, direct compilation and execution of these partitioned subcircuits yields low-fidelity results, highlighting the need for a more holistic optimization strategy.
Circuit knitting is the process of partitioning large quantum circuits into smaller subcircuits such that the result of the original circuits can be deduced by only running the subcircuits. Such techniques will be crucial for near-term and early fault-tolerant quantum computers, as the limited number of qubits is likely to be a major bottleneck for demonstrating quantum advantage. One typically distinguishes between gate cuts and wire cuts when partitioning a circuit. The cost for any circuit knitting approach scales exponentially in the number of cuts. One possibility to realize a cut is via the quasiprobability simulation technique. In fact, we argue that all existing rigorous circuit knitting techniques can be understood in this framework. Furthermore, we characterize the optimal overhead for wire cuts where the subcircuits can exchange classical information or not. We show that the optimal cost for cuttingnwires without and with classical communication between the subcircuits scales asO(16n) andO(4n), respectively.
Quantum circuit cutting enables the execution of large circuits on devices with a limited number of qubits by partitioning circuits into independent subcircuits. However, this introduces a sampling overhead, which grows exponentially with the number of cuts, rendering the choice of cut placements critical for practical circuit cutting. Determining optimal cut placements remains computationally challenging, particularly as circuits grow in size. Additionally, existing circuit cutting approaches typically treat gate and wire cuts independently. Those combining both cutting approaches, however, do not take advantage of joint cutting, i.e., identifying common gate groups and cutting them jointly for a reduced overhead. This work presents a unified framework that combines gate and wire cutting within a single partitioning strategy, enabling more efficient circuit decompositions. Moreover, our approach incorporates joint cutting via a novel gate grouping technique, further reducing sampling overhead. By formulating the cut placement problem as a scalable graph partitioning task, our method efficiently identifies near-optimal cut placements for large circuits, also providing diagnostic feedback on whether circuits are suitable for cutting.
Circuit knitting (see, e.g., [1]) is a technique that allows circuits that are too large to run on a given quantum processing unit (QPU) to be decomposed into an equivalent series of smaller subcircuits that can run on the QPU, where the resulting measurement outcomes of the subcircuits are then classically combined via post-processing. Circuits are decomposed by cutting gates and/or wires. To obtain results to the same accuracy as those of the original problem, each cut incurs additional sampling overhead (denoted γ2) that grows exponentially with the number of cuts. It is therefore desirable to find optimal sets of cuts that minimize the sampling overhead. To this end, we present the “cut-finder” (Sec. I) module of the Circuit Knitting Toolbox (CKT) [2], which performs an automated search for LO gate and wire cuts that minimize the sampling overhead. Circuit knitting can also be used to engineer gates between distant qubits which would otherwise require a large swap overhead to implement. In Sec II, we show how this capability can be used to calculate certain expectation values on a graph state with a cylindrical topology to a better degree of accuracy than if the experiment were to be performed without circuit knitting.
Noise in contemporary quantum hardware is highly non-uniform across qubits and couplers, giving rise to localized low-noise "islands" within otherwise noisy device topologies. As quantum workloads scale, executions are increasingly forced to traverse high-noise regions, degrading algorithmic fidelity. Circuit cutting provides a route to circumvent such regions by decomposing large circuits into smaller subcircuits, but its practicality is limited by exponential sampling overhead and the lack of systematic guidance on how cut strategies should align with heterogeneous hardware noise. In this work, we present a hardware-noise-aware circuit cutting framework that explicitly exploits the spatial non-uniformity of noise in quantum devices. Rather than proposing a new cut-finding algorithm, we formalize the problem of device-constraint selection under realistic hardware noise and show that this choice critically determines both execution overhead and effective noise. Using a unified gate- and wire-cutting formulation, we demonstrate that small, hardware-informed relaxations in the device constraint yield exponential reductions in execution overhead while preserving alignment with low-noise hardware regions. Across representative workloads, our method achieves an average reduction in the number of circuit executions ranging from 5-54x for 20-qubit circuits, and enables tractable circuit cutting for 50-qubit circuits and application-level benchmarks where conventional strategies incur prohibitive overhead. These results establish noise-aware device-constraint selection as a necessary ingredient for making circuit cutting resource-efficient and practically deployable on contemporary quantum hardware.
Executing quantum circuits on current quantum Best Cut Identification devices is fundamentally limited by noise, decoherence, and hardware constraints. Circuit Knitting (CK) techniques enable the execution of larger circuits by decomposing them into smaller sub-circuits, at the cost of reconstruction overhead. At the same time, Quantum Error Mitigation (QEM) methods improve fidelity but introduce additional complexity. In this work, we propose a fidelity-aware framework that jointly optimizes circuit partitioning and error mitigation to maximize end-to-end execution fidelity. We introduce a unified model that captures the trade-off between sub-circuit operational fidelity, reconstruction penalties induced by cuts, and the impact of error mitigation. Based on this model, we formulate the cut placement problem as an optimization task and solve it to identify fidelity-optimal partitioning strategies accounting for error mitigation and under realistic hardware constraints. Notably, our framework integrates calibration-driven noise models and supports practical fidelity estimation using backend-specific parameters. We validate the proposed method on both noisy simulators (IBM Fake Backends) and real quantum hardware (IQM Lagrange), proving consistent improvements in execution fidelity with gains of up to 40% over standard circuit execution.
Near-term hardware is constrained by high error rates, small qubit counts, and relatively low output fidelity, making the execution of large, high performance quantum circuits difficult. Circuit partitioning (or circuit cutting) has emerged as a promising approach to circumvent these limitations by decomposing circuits into smaller subcircuits at two-qubit interaction points. However, it remains unclear which classes of circuits benefit the most from partitioning and under what hardware conditions it is most effective. In this work, we evaluate the suitability of quantum circuits for partitioning from three perspectives: improving fidelity, enabling distributed execution, and scaling to larger circuit sizes. Specifically, we compare uncut circuit execution against two circuit partitioning approaches: Qiskit's automatic cut finding technique and a custom performance optimized circuit cutting method. We also measure these across GHZ, QFT, brickwork, and random quantum circuits ranging from 4 to 14 qubits, using mean absolute error of expectation values and overall output fidelity. Our results show that partitioning benefits larger, highly interconnected circuits, with our custom method reducing error by up to 55\% and improve fidelity for GHZ circuits, but degrading performance for brickwork circuits at larger scales.