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arXiv:2608.28535

Hardware-Efficient Error Mitigation and Shot-Efficient Sampling on IBM Quantum Hardware

Sumit Chongder

quant-phSubmitted Aug 28, 2026• Announced Aug 31, 2026• 0 citations
arXivHTMLPDF

Abstract

We experimentally study error mitigation and finite-shot sampling on superconducting quantum hardware under a constrained execution budget. The study combines calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation on an IBM Quantum processor. Experiments are organized across ideal simulation, noise-model simulation, and physical-device execution to separate sampling uncertainty from device-induced error. We investigate how mitigation performance changes with circuit depth, effective noise scale, qubit connectivity, and measurement budget, and quantify accuracy using expectation-value error, mean-squared error, statistical uncertainty, and mitigation gain. A fixed hardware-execution budget is used to evaluate shot allocation strategies and repeated measurements without relying on unlimited sampling. The resulting analysis provides a hardware-aware characterization of when mitigation improves expectation-value estimation and when finite-shot fluctuations offset the benefit of additional mitigation overhead. The implementation uses contemporary Qiskit and IBM Quantum Runtime workflows and is designed to provide reproducible experimental evidence for error-mitigation studies on current quantum processors.

Comments
16 pages, 9 figures, 6 tables. Experiments performed on IBM Quantum hardware using Qiskit 2.5.0 and Qiskit Runtime 0.48.0. Includes hardware calibration analysis, zero-noise extrapolation, dynamical decoupling, readout mitigation, adaptive shot allocation, repeated hardware experiments, and scaling studies

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We experimentally study error mitigation and finite-shot sampling on superconducting quantum hardware under a constrained execution budget. The study combines calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation on an IBM Quantum processor. Experiments are organized across ideal simulation, noise-model simulation, and physical-device execution to separate sampling uncertainty from device-induced error. We investigate how mitigation performance changes with circuit depth, effective noise scale, qubit connectivity, and measurement budget, and quantify accuracy using expectation-value error, mean-squared error, statistical uncertainty, and mitigation gain. A fixed hardware-execution budget is used to evaluate shot allocation strategies and repeated measurements without relying on unlimited sampling. The resulting analysis provides a hardware-aware characterization of when mitigation improves expectation-value estimation and when finite-shot fluctuations offset the benefit of additional mitigation overhead. The implementation uses contemporary Qiskit and IBM Quantum Runtime workflows and is designed to provide reproducible experimental evidence for error-mitigation studies on current quantum processors.
Abstract Quantum computing has recently emerged as a novel paradigm for solving problems otherwise intractable on classical computers, yet the practical progress of quantum computers is severely impacted by noise, decoherence, and imperfect gate operations in Noisy Intermediate-Scale Quantum (NISQ) devices. Specific to IBM Quantum hardware, imperfections due to readout error, gate errors, and device drift, which depends on time, resolves limits for the accuracy of outputs from our algorithms. The mitigation strategies currently used, for example, Measurement Error Mitigation (MEM), Zero Noise Extrapolation (ZNE), and Clifford Data Regression (CDR), offer improvement over raw, unmitigated outputs, but they are static and not dynamic; the reduction of noise in within an NISQ device is temporal and can vary in patterns that are non-zero. In addition to this, using the conventional methods provides inconsistent and suboptimal results.This study will provide enhanced reliability with respect to performing quantum computation on IBM Quantum hardware with a unique mitigation framework that is adaptive and computationally efficient for a high-fidelity output. The problem taken on here is the failure of existing error mitigation strategies to provide adaptive noise compensation, as they assume a statically-distributed error, despite the performance-related characteristics already being documented in regards to calibration drift and variation over time.To achieve this, we propose a Hybrid Adaptive Error Mitigation (HAEM) approach that includes baseline measurement error mitigation and an additional correction layer that utilizes realtime calibration information, along with lightweight machine learning models. The approach can be broken down into three steps: (i) perform standard measurement error mitigation to reduce classical readout noise, (ii) execute compact calibration circuits, such as Bell states, GHZ states and Clifford benchmarks to capture then current error profile of the device, and (iii) use a lightweight machine learning model (having been trained on historical and newest calibration data) to dynamically change the mitigation weights applied for the target quantum algorithm. All implementation is done using Qiskit Runtime to ensure low-latency execution, and we completed experiments on both Qiskit Aer noisy simulators and IBM Quantum devices.Initial results suggest HAEM improved the outputs of quantum algorithms' fidelity compared to the unmitigated runs and the baseline measurement error mitigation (MEM) runs. On the noisy simulators, HAEM increased fidelity from a raw performance of 0.65 to 0.87, nearly a 34% improvement. In fairer hardware-like scenarios, fidelity-on-average was persistently 12% better than MEM, with nearly equal time duration for the additional adaptive measurements. The adaptive aspect of HAEM consistently supported subsequent calibration cycles of the device and was effective to continue providing fidelity improvements despite the static mitigation performance degrading.To sum up, the proposed HAEM framework is a modern and viable alternative for error mitigation which brings together the benefits of baseline approaches with corrections that are driven by fixed-function error-corrective, adaptive learning. As both learning-based and standard baseline approaches can only achieve fixed levels of performance, HAEM, through its use of noise mitigation both at execution time and through correlating it with standard data, provides a route towards reliable quantum computations on current IBM hardware. HAEM also presents a contribution to the NISQ error-resilient landscape, and however it is intended that it will continue to improve future applications of hybrid workflows of quantum and classical computation where error mitigation and resilience is important.
Readout errors are one of the dominant sources of noise in current quantum processors, limiting both expectation-value estimation and sampling-based applications. Since they affect only the classical measurement outcomes, they can be addressed using classical coding techniques: immediately before measurement, each data qubit is redundantly encoded with ancilla qubits, and the resulting bit string is decoded either by post-selection or by majority voting. Unlike conventional readout error mitigation, which corrects only aggregate quantities such as expectation values, this approach operates on individual measurement shots and can therefore produce approximately corrected samples. We present a systematic cross-platform and cross-generation experimental evaluation of repetition-code readout error detection and correction. We benchmark the same protocol on IBM Heron r1-r3 superconducting processors and Quantinuum H1 and H2 trapped-ion processors while independently varying the code distance, hardware generation, and encoding layout. We find that both error detection and correction improve readout fidelity on every device and generation tested, even as the unencoded baseline improves substantially across successive hardware releases. At the same time, the value of additional redundancy depends strongly on the underlying hardware. On superconducting processors, the extra gate errors introduced by the encoding rapidly offset its benefits, whereas on trapped-ion processors the much lower gate error rates allow larger code distances to remain advantageous.
Quantum error mitigation (QEM) infers noiseless expectation values from noisy variants of a target quantum circuit. Unlike quantum error correction, QEM requires no additional hardware resources and is therefore routinely employed in experiments on contemporary quantum processors. QEM strategies based on agnostic noise amplification (ANA) are intrinsically resilient to temporal noise drift during the execution of the experiment, but their sampling cost (runtime overhead) remains a major practical bottleneck. In this work, we introduce the virtual noise scaling framework and combine it with layered mitigation to further enhance performance. While virtual noise scaling consistently reduces sampling overhead, we identify a specific noise threshold for the layered mitigation approach. When the noise level is above this threshold, layered mitigation decreases the sampling overhead; conversely, when below it, the overhead increases. Notably, this threshold is circuit-independent and depends solely on the number of layers. For strong noise, the combination of virtual noise scaling and layered mitigation yields several orders of magnitude reduction in sampling overhead compared with conventional zero-noise extrapolation post-processing. As a result, mitigation tasks that once seemed unrealistic are now challenging but achievable. The proposed approach is compatible with dynamic circuits and can be seamlessly integrated with error detection and quantum error correction schemes. In addition, it is also applicable to ANA-based mitigation of mid-circuit measurements and preparation errors. Our findings extend to any constant-step amplification factors and therefore also apply to probabilistic error amplification (PEA) QEM. We validate our post-processing approach by applying it to previously reported experimental data, where we observe a substantial improvement in mitigation efficiency and accuracy.
In quantum computing, noisy intermediate-scale quantum (NISQ) devices offer unprecedented computational capabilities but are vulnerable to errors, notably measurement inaccuracies that impact computation accuracy. This study explores the efficacy of error mitigation techniques in improving quantum circuit performance on NISQ devices. Techniques such as dynamic decoupling (DD), twirled readout error extraction (T-REx) and zero-noise extrapolation (ZNE) are examined through extensive experimentation on an ideal simulator, IBM Kyoto, and IBM Osaka quantum computers. Results reveal significant performance discrepancies across scenarios, with error mitigation techniques notably enhancing both estimator result and variance values, aligning more closely with ideal simulator outcomes. The comparison results with ideal simulator (having expected result value 0.8284) shows that T-Rex has improved results on IBM Kyoto and enhanced average expected result value from 0.09 to 0.35. Similarly, DD has improved average expected result values from 0.2492 to 0.3788 on IBM Osaka. These findings underscore the critical role of error mitigation in bolstering quantum computation reliability. The results suggest that selection of mitigation technique depends upon quantum circuit and its depth, type of hardware and operations to be performed.
Assessing whether a noisy quantum device can potentially exhibit quantum advantage is essential for selecting practical quantum utility tasks that are not efficiently verifiable by classical means. For optimization, a prominent candidate for quantum advantage, entropy benchmarking provides insights based concomitantly on the specifics of the application and its implementation, as well as hardware noise. However, such an approach still does not account for finite-shot effects or for quantum error mitigation (QEM), a key near-term error suppression strategy that reduces estimation bias at the cost of increased sampling overhead. We address this limitation by developing a benchmarking framework that explicitly incorporates finite-shot statistics and the resource overhead induced by QEM. Our framework quantifies quantum advantage through the confidence that an estimated energy lies within an interval defined by the best-known classical upper and lower bounds. Using a proof-of-principle numerical study of the two-dimensional Fermi-Hubbard model at size 8×88\times88×8, we demonstrate that the framework effectively identifies noise and shot-budget regimes in which the probabilistic error cancellation (PEC), a representative QEM method, is operationally advantageous, and potential quantum advantage is not hindered by finite-shot effects. Overall, our approach equips end-users with a framework based on lightweight numerics for assessing potential practical quantum advantage in optimization on near-future quantum hardware, in light of the allocated shot budget.
IBM Quantum’s Open Plan currently provides up to 10 minutes of quantum time per 28-day rolling window per instance, making lightweight benchmarking essential for academic users. This paper analyzes the released artifact for a minimal 4-qubit QAOA Max-Cut benchmark executed on ibm_torino. The artifact instantiates the broader agenda of budget-aware mitigation studies as a single-backend, fixed-shot case study: a 4-node ring graph, QAOA depths p ∈ {1, 2}, 2000 shots, and three repeats for each Runtime resilience level r ∈ {0, 1, 2}. We evaluate mitigation quality under an equal-shot budget rather than directly computing error per QPU minute. Two findings emerge. First, mitigation helps primarily on the deeper circuit: for p = 2, mean absolute error falls from 0.399 at level 0 to 0.153 at level 2, a 61.6% reduction. Second, gains are weak and non-monotonic for the shallow p = 1 circuit: level 1 is slightly worse than the unmitigated baseline, while level 2 gives only a modest improvement. A further observation is that the artifact’s Aer device-noise reference is numerically indistinguishable from the ideal statevector reference and therefore does not reproduce the hardware bias seen on the QPU. The results support selective, depth-aware use of mitigation under tight public-access budgets and motivate richer artifact logging for budget-normalized evaluation.