IBM Quantum’s Open Plan currently provides up to 10 minutes of quantum time per 28-day rolling window per instance, making lightweight benchmarking essential for academic users. This paper analyzes the released artifact for a minimal 4-qubit QAOA Max-Cut benchmark executed on ibm_torino. The artifact instantiates the broader agenda of budget-aware mitigation studies as a single-backend, fixed-shot case study: a 4-node ring graph, QAOA depths p ∈ {1, 2}, 2000 shots, and three repeats for each Runtime resilience level r ∈ {0, 1, 2}. We evaluate mitigation quality under an equal-shot budget rather than directly computing error per QPU minute. Two findings emerge. First, mitigation helps primarily on the deeper circuit: for p = 2, mean absolute error falls from 0.399 at level 0 to 0.153 at level 2, a 61.6% reduction. Second, gains are weak and non-monotonic for the shallow p = 1 circuit: level 1 is slightly worse than the unmitigated baseline, while level 2 gives only a modest improvement. A further observation is that the artifact’s Aer device-noise reference is numerically indistinguishable from the ideal statevector reference and therefore does not reproduce the hardware bias seen on the QPU. The results support selective, depth-aware use of mitigation under tight public-access budgets and motivate richer artifact logging for budget-normalized evaluation.
IBM Quantum’s Open Plan currently provides up to 10 minutes of quantum time per 28-day rolling window per instance, making lightweight benchmarking essential for academic users. This paper analyzes the released artifact for a minimal 4-qubit QAOA Max-Cut benchmark executed on ibm_torino. The artifact instantiates the broader agenda of budget-aware mitigation studies as a single-backend, fixed-shot case study: a 4-node ring graph, QAOA depths p ∈ {1, 2}, 2000 shots, and three repeats for each Runtime resilience level r ∈ {0, 1, 2}. We evaluate mitigation quality under an equal-shot budget rather than directly computing error per QPU minute. Two findings emerge. First, mitigation helps primarily on the deeper circuit: for p = 2, mean absolute error falls from 0.399 at level 0 to 0.153 at level 2, a 61.6% reduction. Second, gains are weak and non-monotonic for the shallow p = 1 circuit: level 1 is slightly worse than the unmitigated baseline, while level 2 gives only a modest improvement. A further observation is that the artifact’s Aer device-noise reference is numerically indistinguishable from the ideal statevector reference and therefore does not reproduce the hardware bias seen on the QPU. The results support selective, depth-aware use of mitigation under tight public-access budgets and motivate richer artifact logging for budget-normalized evaluation.
We experimentally study error mitigation and finite-shot sampling on superconducting quantum hardware under a constrained execution budget. The study combines calibration-aware qubit selection, circuit-depth scaling, zero-noise extrapolation, dynamical decoupling, readout-error mitigation, and repeated-shot estimation on an IBM Quantum processor. Experiments are organized across ideal simulation, noise-model simulation, and physical-device execution to separate sampling uncertainty from device-induced error. We investigate how mitigation performance changes with circuit depth, effective noise scale, qubit connectivity, and measurement budget, and quantify accuracy using expectation-value error, mean-squared error, statistical uncertainty, and mitigation gain. A fixed hardware-execution budget is used to evaluate shot allocation strategies and repeated measurements without relying on unlimited sampling. The resulting analysis provides a hardware-aware characterization of when mitigation improves expectation-value estimation and when finite-shot fluctuations offset the benefit of additional mitigation overhead. The implementation uses contemporary Qiskit and IBM Quantum Runtime workflows and is designed to provide reproducible experimental evidence for error-mitigation studies on current quantum processors.
The Quantum Approximate Optimization Algorithm (QAOA) is a leading candidate for near-term quantum advantage in combinatorial optimization. A central design parameter is circuit depth p, with theoretical analyses establishing asymptotic convergence under idealized conditions. This paper presents a limits study demonstrating that this theoretical relationship does not translate to measurable improvement on current noisy intermediate-scale quantum (NISQ) hardware for fault tree analysis applications. Across 120 QAOA executions on 60 QUBO-encoded fault tree instances (N ∈ {12, 16, 20, 24, 28, 32}) on IBM Quantum hardware (ibm_torino, 133-qubit Heron processor), circuit depths p = 1 and p = 2 were directly compared. The mean change in optimal state sampling probability from doubling circuit depth was Δmax_prob = 1.22 × 10⁻⁵ with a median Δ of zero. For 8,192 shots, the binomial sampling uncertainty is O(10⁻²); the observed mean delta is therefore approximately three orders of magnitude below the shot-noise scale, making the difference statistically indistinguishable from zero. Output distribution entropy approaches the theoretical maximum of log₂(8192) ≈ 13 bits, indicating hardware noise dominates algorithmic signal. These findings establish that for fault tree minimal cut set identification on current NISQ devices, computational resources are more effectively allocated to increased shot counts than to circuit depth. Complete experimental artifacts with SHA-256 verification are provided, enabling full reproducibility.
This work evaluates Constraint-Level QUBO (CL-QUBO) circuit execution on IBM Quantum hardware for 34 reactor-scale fault tree subtrees spanning 5–8 basic events, selected from the 776-member quantum-feasible candidate pool established in Paper 9 (Peters, 2026). Circuits were constructed using the CL-QUBO encoding and QAOA Alternating Operator Ansatz at depth p = 1, transpiled to both ibm_torino (133 qubits) and ibm_marrakesh (156 qubits), and executed under three IBM Runtime Sampler configurations (RL0, RL1, RL2) with identical bound parameters (β = 0.2, γ = 0.2) across all resilience levels. A total of six hardware jobs consumed 476 seconds (7.93 minutes) of quantum runtime across 8,192 shots per circuit. The results demonstrate that at this circuit scale, 10–16 logical qubits transpiling to 78–150 two-qubit gates at depths of 165–338, hardware output distributions are overwhelmingly noise-dominated by standard distributional metrics. Neither RL1 nor RL2 produces improvement; RL1 actively degrades output quality relative to RL0 on both backends. However, direct comparison of hardware top-probability outcomes against SCRAM-validated prime implicants from Paper 9 reveals substantial above-random minimal cut set (MCS) enrichment relative to the uniform-random baseline in the n = 8 groups (6.2× and 3.8× expected random rate in the top-200 outcomes), demonstrating that CL-QUBO circuits produce detectable MCS-correlated structure even in distributions that appear noise-dominated by aggregate metrics. These findings characterize the current observed performance ceiling for this CL-QUBO configuration on the tested IBM backends and provide both distributional and MCS-correctness baselines against which future hardware improvements can be measured.
Denial-of-service (DoS) and distributed denial-of-service (DDoS) mitigation requires separating malicious traffic from benign traffic while minimizing disruption to legitimate users. Prior work proposed mapping honeypot traffic partitioning to a weighted MaxCut problem and solving the resulting graphs with variational quantum algorithms. We extend this proof of principle direction with a reproducible event-level honeypot-to-QUBO pipeline, labeled temporal bipartite benchmark graphs with 16, 32, 66, and 110 event nodes, QAOA executions on IBM quantum hardware, classical heuristic baselines, a noiseless matrix product state reference, and a routing overhead analysis across quantum processor architectures. The largest benchmark is a 110-node, 181-edge instance executed on three IBM backends. Our results show that a shallow QAOA can execute real traffic partitioning workloads at the utility scale, while backend architecture and routing overhead affect objective quality, security metrics, and observed runtime. Because simple classical heuristics can solve the current labeled benchmark graphs, these experiments are not a quantum advantage claim. Instead, we deliberately use a fixed, shallow QAOA implementation to enable controlled comparisons across problem sizes and hardware architectures. This work establishes a hardware feasibility and architecture benchmark framework, and demonstrates that MaxCut cost, security quality, routing overhead, and runtime must be reported as separate metrics for cybersecurity relevant quantum optimization.
Abstract Variational quantum algorithms (VQAs) are limited by device noise, and error mitigation is the standard remedy on near-term hardware. Choosing a mitigation method for deployment requires comparing its true cost, yet the usual comparison hides it: it fixes the number of shots per circuit execution, while the methods differ sharply in how many executions they need per estimate. Zero-noise extrapolation (ZNE) needs three to five, Clifford data regression (CDR) more than thirty per target circuit, and a trained neural model exactly one; ZNE's accuracy further rests on a noise-scaling assumption that real devices violate. Inside a variational loop that evaluates thousands of parameter settings, it is this execution multiplicity, not the accuracy at unlimited shots, that decides which method is affordable. Our premise is that the comparison that matters is at equal total shot budget per evaluation point. We present budget-conditioned neural error mitigation (NEM): one network corrects a single shot-limited measurement from circuit and device features, conditioned on the shot-noise scale so that one model serves every budget. We evaluate every method—including each ZNE fold point and each CDR training circuit—under a protocol that spends the same total shots per evaluation point. Under it, NEM is the most accurate method at every budget under coherent miscalibration (reducing error by 72–81%), and the only method that beats unmitigated execution at budgets up to 2^14 shots under stochastic device noise (11–20%); under miscalibration CDR is also positive but overtakes NEM only at 2^16 shots, at 32x the per-evaluation cost. We further characterize when extrapolation fails: under control-offset miscalibration, folding ZNE returns a worse answer than no mitigation on 38–63% of instances in simulation, and on up to 88% on a real IBM Heron processor. On that processor, fine-tuning the model on a small on-device set—120 circuits with classically computed labels—narrows the simulation-to-hardware gap, recovering a 39% error reduction on held-out device instances from the same calibration epoch. Improvements hold from 4 to 20 qubits. Budget-aware accounting, we argue, is the comparison that matters for deployment.
Quantum processors have crossed the one-hundred-qubit mark, but noise continues to limit circuit performance, while full quantum error correction remains too costly for routine use. Error suppression and mitigation therefore play an important role in extracting value from current hardware, yet independent comparisons of commercial solutions on identical workloads and devices remain scarce. We benchmark IBM Qiskit Runtime, Q-CTRL Performance Management, and Qedma QESEM on IBM Pittsburgh, a 156-qubit IBM Quantum Heron r3 processor. For Sampler workloads, we run Bernstein-Vazirani, quantum phase estimation, GHZ-state preparation, and randomized mirror circuits with up to 100 measured qubits, comparing raw execution, IBM measurement twirling, and Q-CTRL. For Estimator workloads, we measure chain-averaged magnetization and correlation observables of an eight-layer transverse-field Ising circuit at 25, 50, and 75 qubits against an exact matrix-product-state reference, comparing IBM raw execution, IBM TREX plus twirling, Q-CTRL, and QESEM. Q-CTRL produced the best results on the three structured Sampler workloads while keeping reported QPU times within the same order as the IBM configurations. Across six Ising observable and system-size cases, aggregate mean absolute error was 0.0883 for IBM raw execution, 0.0807 for IBM TREX plus twirling, 0.0285 for Q-CTRL, and 0.0188 for QESEM. Relative to raw execution, Q-CTRL and QESEM reduced aggregate error by factors of 3.10 and 4.70, respectively, while QESEM used 7.5 to 11.1 times the reported QPU time of Q-CTRL. These results show that managed error suppression and mitigation can substantially improve current hardware performance, but with distinct accuracy and execution-time tradeoffs.