Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

A Cryo-CMOS Fully-Integrated Superconducting Qubit Reflectometry Readout IC with FCNN-Based Adaptive Drift Mitigation and FIR-DSM-Based Stimulus TX

Yanshu Guo, Heyue Li, Xicheng Zhang, Jun Shi, Shijie Yin, Qichun Liu, Ning Deng, Zi Wang, Tiefu Li, G C Wang, Yuanjin Zheng, Hanjun Jiang

Published Jun 14, 2026• 0 citations
Publisher
DOI
10.1109/vlsitechnologyandcir65830.2026.11577211

Related papers

Performance metrics, reliability physics, and error mitigation strategies of cryo-CMOS DACs for superconducting qubit control: A systematic review

Chih-Cheng Chen, Pin-Hua Chen

Microelectronics Reliability•Jun 5, 2026•0 citations

A 65-nm Cryo-CMOS-Based 4–7-GHz Wideband Noise-Canceling Receiver for Superconducting Multi-Qubits Readout

Juhui Jeong, Hyeonsik Ahn, Junhyeop Kim +5 more

IEEE Transactions on Circuits and Systems I Regular Papers•Jan 1, 2026•0 citations

A Fully Integrated CMOS Parametric Amplifier for Cryogenic Qubit Readout

Gabriel López-Pinar, C. Aldea, Santiago Celma +1 more

International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design•Jun 1, 2026•0 citations

28-nm Cryo-CMOS Mixer-First Reflectometer for the FDM Readout of Transmon Qubits

Yujie Geng, Zixin Xu, Tianyu Dong +8 more

IEEE Transactions on Microwave Theory and Techniques•Jul 21, 2026•1 citation

A Cryo-CMOS 4.5~7GHz Dual-Qubit Homodyne Reflectometer Array with High Q Degenerate Parametric Amplifier Through Dynamic Mode Coupling

Yujie Geng, Haichuan Lin, Bo Wang +1 more

Error-corrected quantum computing does not only require large-scale (106–109) physical Qubit arrays but also relies on high-fidelity, scalable quantum-to-classic interface electronics. Quantum control and readout systems based on cryogenic CMOS integrated circuits mitigate the error of Qubit manipulation, reduce the cabling complexity, and facilitate the quantum feedback, which pave the way towards practical quantum error correction (QEC) and logic quantum gates. RF reflectometry is widely adopted for qubit states readout. Reflectometry conducts Qubit states discrimination (collapsed to “0” or “1”) by detecting the resonant frequency through RF reflection of a high-Q LC tank associated with the sensor Qubit (Fig. 1). The quantum states are encoded in either the amplitude or the phase of the reflected RF signal. Compared with its DC counterpart, the reflectometry achieves unprecedented charge sensitivity, reduces the integration time, and avoids long-term drifting. However, conventional heterodyne reflectometer schemes [1][4][5] adopt sophisticated up/down mixers, ADC, DAC, and PLL for the Qubit excitation and down-mixing, respectively. They suffer from poor TX-RX isolation, inter-modulation, and high DC power, which deteriorate the scalability and readout fidelity. To address these challenges, a highly scalable dual-Qubit homodyne reflectometer array is proposed in this paper. It drives the LC tank by a single PLL and detects the reflection by a high-gain degenerate parametric amplifier (DPA). Along with fast modulation and lock-in detection, it mitigates the interference, complex cabling, and high DC power of conventional heterodyne reflectometers.

IEEE Asian Solid-State Circuits Conference (A-SSCC)•Nov 5, 2023•2 citations

A Cryo-CMOS Homodyne-Demodulation Qubit Readout IC With Continuous-Time Analog Integration for SNR Improvement

Donggyu Minn, Kiseo Kang, Jaeho Lee +1 more

This paper presents a homodyne-demodulation readout IC with continuous-time direct analog integration for superconducting qubits. By integration at the analog frontend, the effective signal-to-noise ratio is efficiently increased, eliminating the need for a high-performance analog-to-digital converter and costly baseband processing for data recovery. The proposed IC, fabricated in 40 nm CMOS, is verified at 4 K in a dilution refrigerator. The readout fidelity, estimated under real-world conditions, is reported to be 99% within 300 ns.

IEEE Solid-State Circuits Letters•Jan 1, 2023•6 citations
Error-corrected quantum computing does not only require large-scale (106–109) physical Qubit arrays but also relies on high-fidelity, scalable quantum-to-classic interface electronics. Quantum control and readout systems based on cryogenic CMOS integrated circuits mitigate the error of Qubit manipulation, reduce the cabling complexity, and facilitate the quantum feedback, which pave the way towards practical quantum error correction (QEC) and logic quantum gates. RF reflectometry is widely adopted for qubit states readout. Reflectometry conducts Qubit states discrimination (collapsed to “0” or “1”) by detecting the resonant frequency through RF reflection of a high-Q LC tank associated with the sensor Qubit (Fig. 1). The quantum states are encoded in either the amplitude or the phase of the reflected RF signal. Compared with its DC counterpart, the reflectometry achieves unprecedented charge sensitivity, reduces the integration time, and avoids long-term drifting. However, conventional heterodyne reflectometer schemes [1][4][5] adopt sophisticated up/down mixers, ADC, DAC, and PLL for the Qubit excitation and down-mixing, respectively. They suffer from poor TX-RX isolation, inter-modulation, and high DC power, which deteriorate the scalability and readout fidelity. To address these challenges, a highly scalable dual-Qubit homodyne reflectometer array is proposed in this paper. It drives the LC tank by a single PLL and detects the reflection by a high-gain degenerate parametric amplifier (DPA). Along with fast modulation and lock-in detection, it mitigates the interference, complex cabling, and high DC power of conventional heterodyne reflectometers.
This paper presents a homodyne-demodulation readout IC with continuous-time direct analog integration for superconducting qubits. By integration at the analog frontend, the effective signal-to-noise ratio is efficiently increased, eliminating the need for a high-performance analog-to-digital converter and costly baseband processing for data recovery. The proposed IC, fabricated in 40 nm CMOS, is verified at 4 K in a dilution refrigerator. The readout fidelity, estimated under real-world conditions, is reported to be 99% within 300 ns.