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IEEE Transactions on Microwave Theory and Techniques

28-nm Cryo-CMOS Mixer-First Reflectometer for the FDM Readout of Transmon Qubits

Yujie Geng, Zixin Xu, Tianyu Dong, Yijie Chen, Weichen Wang, Yi Yang, Zhixiao Sun, Ruihong Wu, Haichuan Lin, Mingtang Deng, Cheng Wang

Published Jul 21, 2026• 1 citation
Publisher
DOI
10.1109/tmtt.2026.3712115

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In quantum computers, the quantum state discrimination of the physical quantum bits (Qubits) occupies ~80% of the quantum error correction (QEC) cycle. The RF reflectometry or dispersive readout determines the Qubit state by monitoring the RF reflection of the attached high-Q resonant tank. Compared to their dc counterparts, the RF reflectometers enjoy a high signal-to-noise ratio (SNR), low drifting, and fast speed. As a result, a high-fidelity, single-shot, scalable reflectometer array based on cryogenic CMOS (Cryo-CMOS) ICs is in demand for the future large-scale Qubit array ($10^{3} {\sim } 10^{6}$Qubits). However, the classic Cryo-CMOS heterodyne reflectometers, consisting of MOSFET-based LNA, mixer, and baseband blocks, suffer from high noise temperature and dc power. To address these issues, the Cryo-CMOS parametric circuitry based on varactors is explored. In this article, a dual-Qubit homodyne reflectometer array with 2 RX channels and 1 TX channel is demonstrated. In the RX, the degenerate parametric amplifier (DPA) enjoys a Q-enhanced,$\lambda _{\mathrm { RF}}/2$differential-mode (DM) resonator for the high-gain parametric amplification. The common mode (CM) RF input of DPA interacts with the DM resonator by a nonreciprocal, dynamic mode coupling (DMC). It eliminates the necessity of a circulator and the potential oscillation of DPA. The scalability challenge of the DPA’s noise temperature$T_{\mathrm { noise}}$versus the environment temperature$T_{\mathrm { env}}$is also investigated. In the TX, a current-mode logic (CML) divider with interstate locking and a vector modulator (VM) is implemented to achieve fast modulation for the spur and noise rejection. Measured at 4.2 K, the implemented 65 nm Cryo-CMOS chip presents a$4.5{\sim }7$GHz bandwidth, 52 dB peak RF gain, and 78 K noise temperature, and generates a 10 MHz TX pulse train with -22 dBm RF power and 30 dB tunability. It consumes a total dc power of 33 mW.

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A Cryo-CMOS Demultiplexer for Large-scale Silicon Spin Qubits

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In quantum computers, the quantum state discrimination of the physical quantum bits (Qubits) occupies ~80% of the quantum error correction (QEC) cycle. The RF reflectometry or dispersive readout determines the Qubit state by monitoring the RF reflection of the attached high-Q resonant tank. Compared to their dc counterparts, the RF reflectometers enjoy a high signal-to-noise ratio (SNR), low drifting, and fast speed. As a result, a high-fidelity, single-shot, scalable reflectometer array based on cryogenic CMOS (Cryo-CMOS) ICs is in demand for the future large-scale Qubit array (103∼10610^{3} {\sim } 10^{6}103∼106Qubits). However, the classic Cryo-CMOS heterodyne reflectometers, consisting of MOSFET-based LNA, mixer, and baseband blocks, suffer from high noise temperature and dc power. To address these issues, the Cryo-CMOS parametric circuitry based on varactors is explored. In this article, a dual-Qubit homodyne reflectometer array with 2 RX channels and 1 TX channel is demonstrated. In the RX, the degenerate parametric amplifier (DPA) enjoys a Q-enhanced,λRF/2\lambda _{\mathrm { RF}}/2λRF​/2differential-mode (DM) resonator for the high-gain parametric amplification. The common mode (CM) RF input of DPA interacts with the DM resonator by a nonreciprocal, dynamic mode coupling (DMC). It eliminates the necessity of a circulator and the potential oscillation of DPA. The scalability challenge of the DPA’s noise temperatureTnoiseT_{\mathrm { noise}}Tnoise​versus the environment temperatureTenvT_{\mathrm { env}}Tenv​is also investigated. In the TX, a current-mode logic (CML) divider with interstate locking and a vector modulator (VM) is implemented to achieve fast modulation for the spur and noise rejection. Measured at 4.2 K, the implemented 65 nm Cryo-CMOS chip presents a4.5∼74.5{\sim }74.5∼7GHz bandwidth, 52 dB peak RF gain, and 78 K noise temperature, and generates a 10 MHz TX pulse train with -22 dBm RF power and 30 dB tunability. It consumes a total dc power of 33 mW.