Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at
3−4 K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of
10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at
3−4 K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be
<1 mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion,
4 K receiver for qubit readout that achieves
>1.9GHz of IF bandwidth with
>50 dB conversion gain and
0.7 dB NF while consuming only
17 mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing
3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.
This article presents a cryogenic CMOS receiver operating across 4.7–7.9 GHz for frequency-division multiplexing (FDM) quantum state readout. The designed receiver employs a double quadrature (DQ) architecture and a hybrid poly-phase filter (PPF) is proposed to achieve an impressive image rejection ratio (IRR) to meet the 99.99% higher fidelity requirements in quantum error correction (QEC). In addition, gain tuning at different stages of the low noise amplifier (LNA) facilitates a broadband gain and flatness, while the subsequent receiver chains of a broadband mixer and an improved four-input intermediate frequency amplifier (IF-AMP) provide further gain compensation. Fabricated with a standard 55-nm CMOS technology, the LNA achieves a measured power gain of 27.4 dB, with a −3-dB bandwidth (BW) of 5.2 GHz at 6 K. The measured cryogenic noise figure (NF) ranges from 0.79 to 1 dB consuming merely 5.5 mW from a 1.2-V supply. Overall receiver measurements demonstrate a peak gain of 48.2 dB, a −5-dB flatness of 3.2 GHz, and an IRR that exceeds 40 dB at 6 K. These results demonstrate the receiver’s capacity for high-fidelity qubits’ state readout.