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Microelectronics Reliability

Performance metrics, reliability physics, and error mitigation strategies of cryo-CMOS DACs for superconducting qubit control: A systematic review

Chih-Cheng Chen, Pin-Hua Chen

Published Jun 5, 2026• 0 citations
Publisher
DOI
10.1016/j.microrel.2026.116186

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This article presents a 4 K cryo-CMOS RF-DAC based super-heterodyne transmitter for superconducting-qubit control. The transmitter integrates an RF-DAC based XY-path driver for quantum state manipulation and a current-steering DAC based Z-path driver for flux-bias control. To balance wideband frequency coverage and power consumption, the XY path separates programmable intermediate-frequency (IF) waveform synthesis from final microwave frequency translation. A 10-bit dual-mode RF-DAC first generates wide-IF control pulses, followed by a mixer for up-conversion to the qubit-frequency. By digitally selecting the non-return-to-zero (NRZ) or mixing (MIX) mode according to the target IF range, the RF-DAC exploits different Nyquist zones to extend the usable IF range without proportionally increasing the sampling clock frequency, enabling flexible and FDM-compatible qubit manipulation without increasing too much power. To mitigate RF-DAC current-cell mismatches under cryogenic operation, a mean-absolute-error (MAE)-based foreground calibration technique is proposed. The fully integrated controller is fabricated in a 28-nm CMOS process. The prototype is measured with ~1 GHz IF bandwidth and 8 GHz RF bandwidth under 46 mW power dissipation at the 4-K stage, and it achieves an SFDR of 33.24–41.62 dB within the 4–8 GHz. The ASIC is installed in a dilution refrigerator as a replacement of the classical control instrument, the experiment results further verify the functionality of the ASIC.
Multiple Qubits should be manipulated to perform practical quantum computing, which requires a broad frequency range for the qubit control chip. We present a 4 K cryo-CMOS quantum control chip featuring a Mixing (MIX)/ Non-return-to-zero (NRZ) mode radio frequency digital to analog converter (RF-DAC) and an up-conversion mixer. By opting for Mixing Mode RF-DAC and a mixer for two-stage frequency up-conversion instead of direct-conversion or other methods, our controller can achieve a wider modulated frequency range and lower power consumption.
This paper presents the design and test results of a CMOS current-based Digital to Analog Converter (DAC) that operates at cryogenic temperatures and that can be used to precisely control the amount of flux coupled to qubits or that can be used in the readout of superconducting circuits. The current pulse output can be controlled in terms of its amplitude, rise and fall slopes, via digital controls, and pulse width, via external triggers, while driving a superconducting circuit. The design has been implemented in a planar 90 nm CMOS process and test results closely match circuit predictions. The solution's wide degree of digital tunability affords potential application of the same device to many types of quantum circuits, beyond those discussed here. Due to the wide-ranging flexibility of digital CMOS control, we envision that this DAC design will enable the next generation of high-fidelity cryo-CMOS control architectures for superconducting qubits.
We introduce a superconducting digital-to-analog converter (DAC) that filters control noise, provides native multiplexing, performs quantum gates in nanoseconds, and can be controlled by CMOS. This is achieved by transducing a trapezoidal drive pulse into a superconducting soliton, which is then held in the DAC load loop, applying flux to a mutually-coupled superconducting qubit or gate coupler. The analog flux output by the DAC can be easily controlled by varying the soliton hold time, or with a DC-biased tunable DAC-qubit coupler, allowing the DAC to perform a fixed-time, high-fidelity gate that's robust to fabrication variance or flux offsets in the quantum circuit. Our initial demonstration shows that the DAC can successfully perform 5.6 ns S-gates on transmons. We measure the DAC-induced quantum state excitation probability per gate to be 0.05%, and find that the DAC-induced relaxation rate from the qubit 1 state is below the intrinsic T1 rate limit of the transmon. Quantum simulations show qualitative agreement with the measured data, and predict that the DAC excitation rate can be lowered 10 times further by overdamping the Josephson junction (JJ) in the DAC load loop. may be limited by a Interleaved Randomized Benchmarking (IRB) sequences on an observer qubit reveal that, when scaling to many qubits, the DAC's performance may be limited by a non-local, DAC-induced phase error of 1.6% per gate, appearing in ancilla qubits that are not directly coupled to any of the 30 DACs on the chip. We discuss strategies for future layouts of multi-DAC chips that focus on mitigating the source of these non-local, high-frequency electromagnetic interactions (EMI), and how to incorporate a DC-tunable coupler for phase correction.