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IEEE Transactions on Circuits and Systems I Regular Papers

A Cryo-CMOS Mode-Reconfigurable RF-DAC-Based Super-Heterodyne Transmitter With Mean-Absolute-Error Calibration for Superconducting Qubit Control

Fengen Yuan, Yatao Peng, Hao Su, Yating Zou, Batuhan Keskin, Y.Y. Miao, Wuerkaixi Nuerbolati, Fei Yan, Jun Yin, Rui Paulo Martins, Edoardo Charbon A, Pui‐In Mak

Published Jan 1, 2026• 0 citations
Publisher

Abstract

This article presents a 4 K cryo-CMOS RF-DAC based super-heterodyne transmitter for superconducting-qubit control. The transmitter integrates an RF-DAC based XY-path driver for quantum state manipulation and a current-steering DAC based Z-path driver for flux-bias control. To balance wideband frequency coverage and power consumption, the XY path separates programmable intermediate-frequency (IF) waveform synthesis from final microwave frequency translation. A 10-bit dual-mode RF-DAC first generates wide-IF control pulses, followed by a mixer for up-conversion to the qubit-frequency. By digitally selecting the non-return-to-zero (NRZ) or mixing (MIX) mode according to the target IF range, the RF-DAC exploits different Nyquist zones to extend the usable IF range without proportionally increasing the sampling clock frequency, enabling flexible and FDM-compatible qubit manipulation without increasing too much power. To mitigate RF-DAC current-cell mismatches under cryogenic operation, a mean-absolute-error (MAE)-based foreground calibration technique is proposed. The fully integrated controller is fabricated in a 28-nm CMOS process. The prototype is measured with ~1 GHz IF bandwidth and 8 GHz RF bandwidth under 46 mW power dissipation at the 4-K stage, and it achieves an SFDR of 33.24–41.62 dB within the 4–8 GHz. The ASIC is installed in a dilution refrigerator as a replacement of the classical control instrument, the experiment results further verify the functionality of the ASIC.

DOI
10.1109/tcsi.2026.3735365

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IEEE Journal of Solid-State Circuits•May 27, 2026•1 citation
This article presents a 4 K cryo-CMOS RF-DAC based super-heterodyne transmitter for superconducting-qubit control. The transmitter integrates an RF-DAC based XY-path driver for quantum state manipulation and a current-steering DAC based Z-path driver for flux-bias control. To balance wideband frequency coverage and power consumption, the XY path separates programmable intermediate-frequency (IF) waveform synthesis from final microwave frequency translation. A 10-bit dual-mode RF-DAC first generates wide-IF control pulses, followed by a mixer for up-conversion to the qubit-frequency. By digitally selecting the non-return-to-zero (NRZ) or mixing (MIX) mode according to the target IF range, the RF-DAC exploits different Nyquist zones to extend the usable IF range without proportionally increasing the sampling clock frequency, enabling flexible and FDM-compatible qubit manipulation without increasing too much power. To mitigate RF-DAC current-cell mismatches under cryogenic operation, a mean-absolute-error (MAE)-based foreground calibration technique is proposed. The fully integrated controller is fabricated in a 28-nm CMOS process. The prototype is measured with ~1 GHz IF bandwidth and 8 GHz RF bandwidth under 46 mW power dissipation at the 4-K stage, and it achieves an SFDR of 33.24–41.62 dB within the 4–8 GHz. The ASIC is installed in a dilution refrigerator as a replacement of the classical control instrument, the experiment results further verify the functionality of the ASIC.
Multiple Qubits should be manipulated to perform practical quantum computing, which requires a broad frequency range for the qubit control chip. We present a 4 K cryo-CMOS quantum control chip featuring a Mixing (MIX)/ Non-return-to-zero (NRZ) mode radio frequency digital to analog converter (RF-DAC) and an up-conversion mixer. By opting for Mixing Mode RF-DAC and a mixer for two-stage frequency up-conversion instead of direct-conversion or other methods, our controller can achieve a wider modulated frequency range and lower power consumption.
This article presents a cryogenic transmon qubit state controller integrated circuit (IC) working at a temperature of 3.5 K for superconducting quantum computing (QC) applications. The qubit state controller IC comprises a polar-modulation-based XY -path driver and a current-steering digital-to-analog converter (DAC)-basedZ{Z}Z-path driver. To generate the XY -path driving pulse with arbitrary envelopes in the frequency range of 4–6 GHz, a switched-capacitor digital power amplifier (DPA) is adopted for amplitude modulation, and an injection locking local oscillator (IL-LO) with a constant-slope digital-to-time-converter (DTC) is used for open-loop phase modulation. With the proposed DPA and IL-LO, the controller can control a qubit with a compact architecture. Fabricated in the 28-nm bulk CMOS process, the controller IC occupies an active die area of 0.9 mm2 per driving channel. The controller achieves a spurious-free dynamic range (SFDR) of 40 dB for a 1 GS/s XY -path driver and an SFDR of 48 dB for a 1 GS/sZ{Z}Z-path driver at 3.5 K. The controller consumes a power of 13.7 mW per qubit. A Rabi experiment at 13.9 MHz, a Ramsey experiment at 3.09 MHz, and a T1 experiment at 15.87μs\mu \text{s}μsare conducted using the presented controller IC at 3.5 K to control the transmon superconducting qubit at 10 mK directly.
This paper presents the design and test results of a CMOS current-based Digital to Analog Converter (DAC) that operates at cryogenic temperatures and that can be used to precisely control the amount of flux coupled to qubits or that can be used in the readout of superconducting circuits. The current pulse output can be controlled in terms of its amplitude, rise and fall slopes, via digital controls, and pulse width, via external triggers, while driving a superconducting circuit. The design has been implemented in a planar 90 nm CMOS process and test results closely match circuit predictions. The solution's wide degree of digital tunability affords potential application of the same device to many types of quantum circuits, beyond those discussed here. Due to the wide-ranging flexibility of digital CMOS control, we envision that this DAC design will enable the next generation of high-fidelity cryo-CMOS control architectures for superconducting qubits.
Building a large-scale quantum computer requires the co-optimization of both the quantum bits (qubits) and their control electronics. By operating the CMOS control circuits at cryogenic temperatures (cryo-CMOS), and hence in close proximity to the cryogenic solid-state qubits, a compact quantum-computing system can be achieved, thus promising scalability to the large number of qubits required in a practical application. This work presents a cryo-CMOS microwave signal generator for frequency-multiplexed control of 4 × 32 qubits (32 qubits per RF output). A digitally intensive architecture offering full programmability of phase, amplitude, and frequency of the output microwave pulses and a wideband RF front end operating from 2 to 20 GHz allow targeting both spin qubits and transmons. The controller comprises a qubit-phase-tracking direct digital synthesis (DDS) back end for coherent qubit control and a single-sideband (SSB) RF front end optimized for minimum leakage between the qubit channels. Fabricated in Intel 22-nm FinFET technology, it achieves a 48-dB SNR and 45-dB spurious-free dynamic range (SFDR) in a 1-GHz data bandwidth when operating at 3 K, thus enabling high-fidelity qubit control. By exploiting the on-chip 4096-instruction memory, the capability to translate quantum algorithms to microwave signals has been demonstrated by coherently controlling a spin qubit at both 14 and 18 GHz.
In today's mainstream superconducting quantum computing platforms in a dilution refrigerator, the qubits work at a cryogenic temperature (CT) of a few tens of mK, while the qubit controller hardware works on plates with temperature ranging from a few K to room temperature (RT). The highly-integrated cryo-CMOS qubit controller ASIC that can fully work at 3-4K has been proven to be the most feasible way to scale down the quantum computing system [1–5]. In [1], a pulse modulator is implemented with a limited qubit driving capability, which can only generate fixed length symmetric driving pulse. The controllers in [2], [3] generated the RF driving pulse with a frequency division multiplexing (FDM) mode, with the power dissipation of 192mW/qubit and 46.5mW/qubit, respectively. In [4], a local oscillator (LO) was included to improve the controller integration level, and the chip power consumption was 24.1mW/qubit. An arbitrary waveform generation (AWG) functionality digital design was presented in [5] with a power consumption of 23.1mW/qubit. Nevertheless, with continuously increasing number of qubits to integrate, it remains as one of the major tasks to further reduce the power consumption and size of controller.
This article presents a cryogenic quantum interface chipset at 3.5 K for superconducting transmon qubit operations. The chipset comprises a phase-detection readout and a phase-shifter-based polar-modulation controller with flexible scalability. With the proposed phase-detection readout scheme, a 9-bit time-to-digital converter (TDC)-based state detector is used to read out the qubit state by detecting the phase difference between the stimulus signal and the reflected signal. A low-IF N-path filter-based receiver and a multi-tone transmitter are co-designed to enable frequency-division multiplexing (FDM) dispersive readout of multiple qubits. A phase-shifter-based polar-modulation XY-driver is developed with support for fast phase quantum gate operation and derivative-removal-by-adiabatic-gate (DRAG) pulse generation. The Z-driver is realized using a static digital-to-analog converter (DAC) array and a 10-bit dynamic DAC for power efficiency. Fabricated in a 28-nm bulk CMOS process, the chipset occupies a die area of 4.6 mm2. The readout RX achieves a noise temperature of 40 K with a gain of 45–83 dB and a bandwidth of 1.2 GHz. The readout RX consumes 32% less power than state-of-the-art designs. The measured total readout power for simultaneous detection of two qubits is 12.2 mW, which is the lowest among readouts with a similar integration level. In addition, the controller achieves a spurious-free dynamic range (SFDR) of 49 dB for a 1-GS/s Z-driver and an SNR of 42 dB for a 1-GS/s XY-driver. The XY-driver consumes 4.3 mW per qubit under active control. Verified with practical transmon qubits, the readout fidelity exceeds 92.6%, approaching that of commercial instruments. A Rabi experiment at 5.61/6.36 MHz, a Ramsey experiment at 4.1 MHz, and a T1 experiment at9.98 μ9.98~{\mu }9.98 μs are also successfully observed using the proposed chipset at 3.5 K.