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Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

A Polar-Modulation-Based Cryogenic Qubit State Controller in 28nm Bulk CMOS

Yanshu Guo, Yaoyu Li, Wenqiang Huang, Songyao Tan, Qichun Liu, Tiefu Li, Ning Deng, Zhihua Wang, Yuanjin Zheng, Hanjun Jiang

Published Feb 19, 2023• 25 citations
Publisher

Abstract

In today's mainstream superconducting quantum computing platforms in a dilution refrigerator, the qubits work at a cryogenic temperature (CT) of a few tens of mK, while the qubit controller hardware works on plates with temperature ranging from a few K to room temperature (RT). The highly-integrated cryo-CMOS qubit controller ASIC that can fully work at 3-4K has been proven to be the most feasible way to scale down the quantum computing system [1–5]. In [1], a pulse modulator is implemented with a limited qubit driving capability, which can only generate fixed length symmetric driving pulse. The controllers in [2], [3] generated the RF driving pulse with a frequency division multiplexing (FDM) mode, with the power dissipation of 192mW/qubit and 46.5mW/qubit, respectively. In [4], a local oscillator (LO) was included to improve the controller integration level, and the chip power consumption was 24.1mW/qubit. An arbitrary waveform generation (AWG) functionality digital design was presented in [5] with a power consumption of 23.1mW/qubit. Nevertheless, with continuously increasing number of qubits to integrate, it remains as one of the major tasks to further reduce the power consumption and size of controller.

DOI
10.1109/isscc42615.2023.10067495

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In today's mainstream superconducting quantum computing platforms in a dilution refrigerator, the qubits work at a cryogenic temperature (CT) of a few tens of mK, while the qubit controller hardware works on plates with temperature ranging from a few K to room temperature (RT). The highly-integrated cryo-CMOS qubit controller ASIC that can fully work at 3-4K has been proven to be the most feasible way to scale down the quantum computing system [1–5]. In [1], a pulse modulator is implemented with a limited qubit driving capability, which can only generate fixed length symmetric driving pulse. The controllers in [2], [3] generated the RF driving pulse with a frequency division multiplexing (FDM) mode, with the power dissipation of 192mW/qubit and 46.5mW/qubit, respectively. In [4], a local oscillator (LO) was included to improve the controller integration level, and the chip power consumption was 24.1mW/qubit. An arbitrary waveform generation (AWG) functionality digital design was presented in [5] with a power consumption of 23.1mW/qubit. Nevertheless, with continuously increasing number of qubits to integrate, it remains as one of the major tasks to further reduce the power consumption and size of controller.
Cryogenic CMOS (Cryo-CMOS) ASICs have drawn increasing attention with great potential in scaling down the quantum computing (QC) platform. Recently, several cryoCMOS ASICs have been presented in the literature, including the qubit state readout ASICs [1–4] and state controller ASICs [5–8]. For readout ASICs, the quadrature down conversion architecture is widely adopted, with the power consumption ranging from 20mW [1] to 75mW [2]. Also, significant progress has been made in reducing the power consumption of qubit controllers. The controller in [5] consumes a power of <4 mW/qubit under active control, when controlling a superconducting quantum computing unit cell. Nevertheless, it remains a long-term goal to reduce the power consumption and promote the integration level of readout/controller ASICs, in consideration of the increasing requirement on qubit number and the limited cooling power provided by the dilution refrigerator.
Quantum computing promises exponential speed-up in solving certain complex problems that would be intractable by classical computers. However, thousands or millions of qubits might be required to solve useful problems. High-precision and low-noise electrical signals are required to manipulate and read the state of a qubit and to control qubit-to-qubit interactions. Current systems use room temperature electronics with many coax cables routed to the qubit chip inside a dilution refrigerator. This approach does not scale to large number of qubits, due to form factor, cost, power consumption and thermal load to the fridge. To address this challenge, a cryogenic qubit controller has been proposed [1]. The first integrated implementation of a cryogenic pulse modulator has been presented in [2], demonstrating the capability of manipulating (drive) the state of superconducting qubits. The work in [3] extends the capability of the controller with 3 main features: frequency-multiplexing to reduce the number of RF cables per qubit, an arbitrary I/Q pulse generation for improved control fidelity and a digitally-intensive architecture with integrated instruction set to enable integration in existing quantum control stacks. This work further advances the prior art by integrating the capability of reading the qubit state and generating the voltage pulses required for drive, readout, 2-qubit operations and qubit characterization. The SoC can drive up to 16 spin qubits by frequency multiplexing over a single RF line, read the state of up to 6 qubits simultaneously and control up to 22 gate potentials. The SoC also integrates a μ\muμ-controller for increased flexibility in implementing the control instruction set. The proposed cryogenic controller can replace all the high-speed control electronics used in conventional solutions today, paving the way towards scalable quantum computers.
Extensive research on quantum mechanics in past decades has successfully paved the way towards the disruptive technology of quantum computing. A further step to the realization of a fault-tolerant scalable quantum computer is presenting challenges in the field of engineering. It necessitates a microsystem operating at 4K in a dilution refrigerator, which would be inevitable to control thousands or millions of qubits sitting at 10mK. There have been IC implementations of pulse modulators generating qubit-controlling microwave signals [1– 4]. The pulse modulation based on direct synthesis demonstrated feasibility of driving multiple qubits with frequency-division multiplexing (FDM) through one RF cable [1 – 3]. The first implementation of a full controller [1], which includes both read and write chains for spin qubits, demonstrated the highest level of integration. However, the previous work used external local oscillator (LO) sources for frequency synthesis. External feeding of LO requires precise matching; otherwise, a failure would cause leakage to the qubit driving output through PCB traces, resulting in AC-Stark shift of qubit state by unwanted tones at near-resonance. It becomes more problematic in FDM-based multi-qubit driving. Since the fidelity of qubit operations strongly relies on the quality of driving frequency, a low-noise LO generation by a phase-locked loop (PLL) is one of the most important factors [5]. The internal generation of LO gives additional benefits in superconducting qubit interface. It necessitates multiple LOs since the superconducting qubit uses microwave pulse driving for both read and write. To detect the state of a qubit through dispersive readout, the phase reflected from the readout resonator should be measured. Therefore, the driving pulses for the read and the write should be synchronized to a single reference timing. Using built-in PLLs sharing a single reference clock naturally solves this problem.
This article presents a cryogenic transmon qubit state controller integrated circuit (IC) working at a temperature of 3.5 K for superconducting quantum computing (QC) applications. The qubit state controller IC comprises a polar-modulation-based XY -path driver and a current-steering digital-to-analog converter (DAC)-basedZ{Z}Z-path driver. To generate the XY -path driving pulse with arbitrary envelopes in the frequency range of 4–6 GHz, a switched-capacitor digital power amplifier (DPA) is adopted for amplitude modulation, and an injection locking local oscillator (IL-LO) with a constant-slope digital-to-time-converter (DTC) is used for open-loop phase modulation. With the proposed DPA and IL-LO, the controller can control a qubit with a compact architecture. Fabricated in the 28-nm bulk CMOS process, the controller IC occupies an active die area of 0.9 mm2 per driving channel. The controller achieves a spurious-free dynamic range (SFDR) of 40 dB for a 1 GS/s XY -path driver and an SFDR of 48 dB for a 1 GS/sZ{Z}Z-path driver at 3.5 K. The controller consumes a power of 13.7 mW per qubit. A Rabi experiment at 13.9 MHz, a Ramsey experiment at 3.09 MHz, and a T1 experiment at 15.87μs\mu \text{s}μsare conducted using the presented controller IC at 3.5 K to control the transmon superconducting qubit at 10 mK directly.
This article presents a fully integrated Cryo-CMOS system on chip (SoC) for quantum computing. The proposed SoC integrates a radio frequency (RF) pulse modulator for qubit state manipulation, a multi-tone signal generator and a coherent receiver for qubit state readout, and 22 DACs for high-speed voltage pulsing of qubit gates. By adopting frequency division multiplexing and direct digital synthesis (DDS), the RF pulse modulator can control up to 16 qubits over a single RF line, and the readout receiver can detect the state of up to six qubits simultaneously. The proposed SoC also integrates a microcontroller for low latency on-chip signal processing and increased flexibility in implementing quantum instruction sets. A detailed analysis of qubit-state readout fidelity and the impact of finite DAC resolution on two-qubit gate fidelity is also included in this article, together with an electrical specification summary. The SoC is implemented in Intel’s 22 nm FFL fin field-effect transistor (FinFET) process, and it is characterized both at room and 4 K temperatures. The performance of each specific block is measured, with the readout characterized in a loop-back configuration. Generation of the control signals required for a full Rabi oscillation experiment is also demonstrated. This article also describes the cryogenic thermalization techniques used to integrate the SoC in the dilution refrigerator and shows temperature measurements during operation.
Today’s quantum computing systems rely on commercial electronics operating at room temperature in order to perform control and readout operations for qubits [1] –[6]. The qubits operate at cryogenic temperatures; the signals that support control and readout of qubits therefore traverse multiple temperature stages in a dilution refrigerator to enable interaction with the qubits of a quantum computer. For many of the most advanced quantum computers built to date, the control of each individual qubit demands application of a radiofrequency pulse that is precisely calibrated in frequency, amplitude, and phase. Oubit readout demands the amplification of very low amplitude signals that are then post-processed to categorize the state of the qubit being measured. Oubit control electronics are implemented using arbitrary waveform generators (AWGs) of various types. The scalability of such systems is challenged by the need to scale the number of qubit control electronics units linearly with the number of qubits in the system. One approach to mitigating this challenge that is under active exploration is the use of multi-channel AWGs (tailored to the requirements of qubit control) that operate at the 4K stage of a quantum computing system [7] –[10]. Oubit readout electronics are typically implemented using multiple stages of amplification and then DSP-based readout performed at room temperature. In today’s systems, while readout electronics benefits from multiplexing of the readout signals (enabling a single cascade of moderately wideband amplifiers to support the delivery of multiple readout signals to the room-temperature electronics), again, the scalability of this approach is challenged much as is the case with control electronics. One approach to mitigating the readout challenge is the expanded use of cryogenic electronics in the readout chain. Success in the implementation of cryogenic control and readout solutions depends critically on multiple CMOS sub-components; in this paper we focus on SRAM and low noise amplifiers (LNAs). Note that SRAM is critical for both control and readout applications as a mixed-signal solution involving the combination of a custom processor and analog elements is highly desirable in both cases. Further, while the LNA is directly used as an element in the readout chain, a deep assessment of LNA performance and opportunities strongly benefits overall understanding of achievable noise performance in CMOS technologies at cryogenic temperatures and is therefore impoitant in both control and readout contexts.