Cryogenic CMOS (Cryo-CMOS) ASICs have drawn increasing attention with great potential in scaling down the quantum computing (QC) platform. Recently, several cryoCMOS ASICs have been presented in the literature, including the qubit state readout ASICs [1–4] and state controller ASICs [5–8]. For readout ASICs, the quadrature down conversion architecture is widely adopted, with the power consumption ranging from 20mW [1] to 75mW [2]. Also, significant progress has been made in reducing the power consumption of qubit controllers. The controller in [5] consumes a power of <4 mW/qubit under active control, when controlling a superconducting quantum computing unit cell. Nevertheless, it remains a long-term goal to reduce the power consumption and promote the integration level of readout/controller ASICs, in consideration of the increasing requirement on qubit number and the limited cooling power provided by the dilution refrigerator.
In today's mainstream superconducting quantum computing platforms in a dilution refrigerator, the qubits work at a cryogenic temperature (CT) of a few tens of mK, while the qubit controller hardware works on plates with temperature ranging from a few K to room temperature (RT). The highly-integrated cryo-CMOS qubit controller ASIC that can fully work at 3-4K has been proven to be the most feasible way to scale down the quantum computing system [1–5]. In [1], a pulse modulator is implemented with a limited qubit driving capability, which can only generate fixed length symmetric driving pulse. The controllers in [2], [3] generated the RF driving pulse with a frequency division multiplexing (FDM) mode, with the power dissipation of 192mW/qubit and 46.5mW/qubit, respectively. In [4], a local oscillator (LO) was included to improve the controller integration level, and the chip power consumption was 24.1mW/qubit. An arbitrary waveform generation (AWG) functionality digital design was presented in [5] with a power consumption of 23.1mW/qubit. Nevertheless, with continuously increasing number of qubits to integrate, it remains as one of the major tasks to further reduce the power consumption and size of controller.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at
3−4 K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of
10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at
3−4 K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be
<1 mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion,
4 K receiver for qubit readout that achieves
>1.9GHz of IF bandwidth with
>50 dB conversion gain and
0.7 dB NF while consuming only
17 mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing
3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.
Quantum computing promises exponential speed-up in solving certain complex problems that would be intractable by classical computers. However, thousands or millions of qubits might be required to solve useful problems. High-precision and low-noise electrical signals are required to manipulate and read the state of a qubit and to control qubit-to-qubit interactions. Current systems use room temperature electronics with many coax cables routed to the qubit chip inside a dilution refrigerator. This approach does not scale to large number of qubits, due to form factor, cost, power consumption and thermal load to the fridge. To address this challenge, a cryogenic qubit controller has been proposed [1]. The first integrated implementation of a cryogenic pulse modulator has been presented in [2], demonstrating the capability of manipulating (drive) the state of superconducting qubits. The work in [3] extends the capability of the controller with 3 main features: frequency-multiplexing to reduce the number of RF cables per qubit, an arbitrary I/Q pulse generation for improved control fidelity and a digitally-intensive architecture with integrated instruction set to enable integration in existing quantum control stacks. This work further advances the prior art by integrating the capability of reading the qubit state and generating the voltage pulses required for drive, readout, 2-qubit operations and qubit characterization. The SoC can drive up to 16 spin qubits by frequency multiplexing over a single RF line, read the state of up to 6 qubits simultaneously and control up to 22 gate potentials. The SoC also integrates a
μ-controller for increased flexibility in implementing the control instruction set. The proposed cryogenic controller can replace all the high-speed control electronics used in conventional solutions today, paving the way towards scalable quantum computers.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.
This article presents a cryogenic quantum interface chipset at 3.5 K for superconducting transmon qubit operations. The chipset comprises a phase-detection readout and a phase-shifter-based polar-modulation controller with flexible scalability. With the proposed phase-detection readout scheme, a 9-bit time-to-digital converter (TDC)-based state detector is used to read out the qubit state by detecting the phase difference between the stimulus signal and the reflected signal. A low-IF N-path filter-based receiver and a multi-tone transmitter are co-designed to enable frequency-division multiplexing (FDM) dispersive readout of multiple qubits. A phase-shifter-based polar-modulation XY-driver is developed with support for fast phase quantum gate operation and derivative-removal-by-adiabatic-gate (DRAG) pulse generation. The Z-driver is realized using a static digital-to-analog converter (DAC) array and a 10-bit dynamic DAC for power efficiency. Fabricated in a 28-nm bulk CMOS process, the chipset occupies a die area of 4.6 mm2. The readout RX achieves a noise temperature of 40 K with a gain of 45–83 dB and a bandwidth of 1.2 GHz. The readout RX consumes 32% less power than state-of-the-art designs. The measured total readout power for simultaneous detection of two qubits is 12.2 mW, which is the lowest among readouts with a similar integration level. In addition, the controller achieves a spurious-free dynamic range (SFDR) of 49 dB for a 1-GS/s Z-driver and an SNR of 42 dB for a 1-GS/s XY-driver. The XY-driver consumes 4.3 mW per qubit under active control. Verified with practical transmon qubits, the readout fidelity exceeds 92.6%, approaching that of commercial instruments. A Rabi experiment at 5.61/6.36 MHz, a Ramsey experiment at 4.1 MHz, and a T1 experiment at
9.98 μs are also successfully observed using the proposed chipset at 3.5 K.
Quantum computing holds the promise to solve many of today's intractable problems. A solid-state quantum computer (QC) is generally made of an array of qubits implemented in one of many solid-state technologies and operating at deep-cryogenic temperatures (10-to-20mK). Silicon spin qubits are a promising candidate for scalable QCs, due to their size, long coherence times and potential for co-integration with the required classical control and readout electronics. Recently, semiconductor spin qubits have been demonstrated to operate at ~1K, thus accelerating the achievement of a compact QC [1]. Classical qubit control electronics has also progressed, with the demonstration of fully-integrated control of spin qubits [2] and transmons [3] implemented in a cryo-CMOS technology. While a cryo-CMOS integrated circuit has been co-integrated with quantum dots [4], fully-integrated readout electronics has not yet been addressed in the literature.