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IEEE Asian Solid-State Circuits Conference (A-SSCC)

A Cryo-CMOS 4.5~7GHz Dual-Qubit Homodyne Reflectometer Array with High Q Degenerate Parametric Amplifier Through Dynamic Mode Coupling

Yujie Geng, Haichuan Lin, Bo Wang, Cheng Wang

Published Nov 5, 2023• 2 citations
Publisher

Abstract

Error-corrected quantum computing does not only require large-scale (106–109) physical Qubit arrays but also relies on high-fidelity, scalable quantum-to-classic interface electronics. Quantum control and readout systems based on cryogenic CMOS integrated circuits mitigate the error of Qubit manipulation, reduce the cabling complexity, and facilitate the quantum feedback, which pave the way towards practical quantum error correction (QEC) and logic quantum gates. RF reflectometry is widely adopted for qubit states readout. Reflectometry conducts Qubit states discrimination (collapsed to “0” or “1”) by detecting the resonant frequency through RF reflection of a high-Q LC tank associated with the sensor Qubit (Fig. 1). The quantum states are encoded in either the amplitude or the phase of the reflected RF signal. Compared with its DC counterpart, the reflectometry achieves unprecedented charge sensitivity, reduces the integration time, and avoids long-term drifting. However, conventional heterodyne reflectometer schemes [1][4][5] adopt sophisticated up/down mixers, ADC, DAC, and PLL for the Qubit excitation and down-mixing, respectively. They suffer from poor TX-RX isolation, inter-modulation, and high DC power, which deteriorate the scalability and readout fidelity. To address these challenges, a highly scalable dual-Qubit homodyne reflectometer array is proposed in this paper. It drives the LC tank by a single PLL and detects the reflection by a high-gain degenerate parametric amplifier (DPA). Along with fast modulation and lock-in detection, it mitigates the interference, complex cabling, and high DC power of conventional heterodyne reflectometers.

DOI
10.1109/a-sscc58667.2023.10347990

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Error-corrected quantum computing does not only require large-scale (106–109) physical Qubit arrays but also relies on high-fidelity, scalable quantum-to-classic interface electronics. Quantum control and readout systems based on cryogenic CMOS integrated circuits mitigate the error of Qubit manipulation, reduce the cabling complexity, and facilitate the quantum feedback, which pave the way towards practical quantum error correction (QEC) and logic quantum gates. RF reflectometry is widely adopted for qubit states readout. Reflectometry conducts Qubit states discrimination (collapsed to “0” or “1”) by detecting the resonant frequency through RF reflection of a high-Q LC tank associated with the sensor Qubit (Fig. 1). The quantum states are encoded in either the amplitude or the phase of the reflected RF signal. Compared with its DC counterpart, the reflectometry achieves unprecedented charge sensitivity, reduces the integration time, and avoids long-term drifting. However, conventional heterodyne reflectometer schemes [1][4][5] adopt sophisticated up/down mixers, ADC, DAC, and PLL for the Qubit excitation and down-mixing, respectively. They suffer from poor TX-RX isolation, inter-modulation, and high DC power, which deteriorate the scalability and readout fidelity. To address these challenges, a highly scalable dual-Qubit homodyne reflectometer array is proposed in this paper. It drives the LC tank by a single PLL and detects the reflection by a high-gain degenerate parametric amplifier (DPA). Along with fast modulation and lock-in detection, it mitigates the interference, complex cabling, and high DC power of conventional heterodyne reflectometers.
In quantum computers, the quantum state discrimination of the physical quantum bits (Qubits) occupies ~80% of the quantum error correction (QEC) cycle. The RF reflectometry or dispersive readout determines the Qubit state by monitoring the RF reflection of the attached high-Q resonant tank. Compared to their dc counterparts, the RF reflectometers enjoy a high signal-to-noise ratio (SNR), low drifting, and fast speed. As a result, a high-fidelity, single-shot, scalable reflectometer array based on cryogenic CMOS (Cryo-CMOS) ICs is in demand for the future large-scale Qubit array (103∼10610^{3} {\sim } 10^{6}103∼106Qubits). However, the classic Cryo-CMOS heterodyne reflectometers, consisting of MOSFET-based LNA, mixer, and baseband blocks, suffer from high noise temperature and dc power. To address these issues, the Cryo-CMOS parametric circuitry based on varactors is explored. In this article, a dual-Qubit homodyne reflectometer array with 2 RX channels and 1 TX channel is demonstrated. In the RX, the degenerate parametric amplifier (DPA) enjoys a Q-enhanced,λRF/2\lambda _{\mathrm { RF}}/2λRF​/2differential-mode (DM) resonator for the high-gain parametric amplification. The common mode (CM) RF input of DPA interacts with the DM resonator by a nonreciprocal, dynamic mode coupling (DMC). It eliminates the necessity of a circulator and the potential oscillation of DPA. The scalability challenge of the DPA’s noise temperatureTnoiseT_{\mathrm { noise}}Tnoise​versus the environment temperatureTenvT_{\mathrm { env}}Tenv​is also investigated. In the TX, a current-mode logic (CML) divider with interstate locking and a vector modulator (VM) is implemented to achieve fast modulation for the spur and noise rejection. Measured at 4.2 K, the implemented 65 nm Cryo-CMOS chip presents a4.5∼74.5{\sim }74.5∼7GHz bandwidth, 52 dB peak RF gain, and 78 K noise temperature, and generates a 10 MHz TX pulse train with -22 dBm RF power and 30 dB tunability. It consumes a total dc power of 33 mW.
Extensive research on quantum mechanics in past decades has successfully paved the way towards the disruptive technology of quantum computing. A further step to the realization of a fault-tolerant scalable quantum computer is presenting challenges in the field of engineering. It necessitates a microsystem operating at 4K in a dilution refrigerator, which would be inevitable to control thousands or millions of qubits sitting at 10mK. There have been IC implementations of pulse modulators generating qubit-controlling microwave signals [1– 4]. The pulse modulation based on direct synthesis demonstrated feasibility of driving multiple qubits with frequency-division multiplexing (FDM) through one RF cable [1 – 3]. The first implementation of a full controller [1], which includes both read and write chains for spin qubits, demonstrated the highest level of integration. However, the previous work used external local oscillator (LO) sources for frequency synthesis. External feeding of LO requires precise matching; otherwise, a failure would cause leakage to the qubit driving output through PCB traces, resulting in AC-Stark shift of qubit state by unwanted tones at near-resonance. It becomes more problematic in FDM-based multi-qubit driving. Since the fidelity of qubit operations strongly relies on the quality of driving frequency, a low-noise LO generation by a phase-locked loop (PLL) is one of the most important factors [5]. The internal generation of LO gives additional benefits in superconducting qubit interface. It necessitates multiple LOs since the superconducting qubit uses microwave pulse driving for both read and write. To detect the state of a qubit through dispersive readout, the phase reflected from the readout resonator should be measured. Therefore, the driving pulses for the read and the write should be synchronized to a single reference timing. Using built-in PLLs sharing a single reference clock naturally solves this problem.
Main-stream quantum computers employ dispersive reflectometry for quantum-bit (Qubit) state discrimination. An all-parametric quantum reflectometer (APQR) scheme has been proposed for high-fidelity, scalable Qubit array readout in this letter. For the RF excitation of APQR, a 10.7–16.9 GHz 65-nm cryogenic CMOS (Cryo-CMOS) parametric frequency divider (PFD) is demonstrated here. It adopts a pair of parallelly connected nonlinear artificial transmission lines (NLATLs), a wideband varactor-based dynamic coupler, and a transformer-based CM filter (TCMF). Due to the minimized device self-heating without dc power consumption and the intrinsic common-mode (CM) to differential-mode (DM) isolation, the PFD presents a measured output thermal noise floor of −189.1 dBm/Hz at 4.2 K. This is only 3.3 dB higher than 4.2-K blackbody radiation. At 4.2 K, the PFD also exhibits an ultralow phase noise of −128.8 dBc/Hz at 1 MHz at 6.75 GHz, which is 2.6 dB lower than a conventional Cryo-CMOS CML divider. It presents a 44.9% relative bandwidth at 4.2 K, which is$2\times $of the prior art at 300 K.
Continuous rounds of quantum error correction (QEC) are essential to achieve fault-tolerant quantum computers (QCs). In each QEC cycle, thousands of ancilla quantum bits (qubits) must be read out faster than the qubits’ decoherence time (≫T2∗∼120μs(\gg \mathrm{T}_{2} * \sim 120 \mu \mathrm{s}(≫T2​∗∼120μs for spin qubits). To address this urgent need, several CMOS receivers operating at cryogenic temperatures (cryo-CMOS RXs) have recently been introduced for gate-based [1] and RF reflectometry [2] readout of spin qubits, as well as transmons’ dispersive readout [3]. However, they have a few shortcomings. First, due to the temperature-independent shot noise of transistors in nanometer CMOS technology [4], their measured noise temperature (TN)(\mathrm{T}_{{\mathrm {N}}})(TN​) is limited to 40K, thus degrading qubit readout fidelity. Second, due to their large TN, prior art showed either only the electrical performance of their chips by applying a relatively large (i.e., -85dBm [2]) modulated signal directly to the RX input [2, 3] or offered limited qubit measurements by exploiting a HEMT amplifier prior to the RX [1]. Those issues hinder future monolithic integration between solid-state qubits and readout electronics. This work advances the prior art by (1) introducing a wideband passive amplification circuit at the RX front-end to minimize the shot noise contribution of the active devices, lowering prior art TNby ∼2.7x\sim 2.7\mathrm{x}∼2.7x; (2) demonstrating the RX performance in an RF-reflectometry qubit readout scheme without using off-the-shelf LNA prior to the RX.
A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3digitally controlled oscillator required to manipulate the state of qubits.
In this paper, we provide a system level perspective on the design of control electronics for large scale quantum systems. Quantum computing systems with high-fidelity control and readout, coherent coupling, calibrated gates, and reconfigurable circuits with low error rates are expected to have superior quantum volumes. Cryogenic CMOS plays a crucial role in the realization of scalable quantum computers, by minimizing the feature size, lowering the cost, power consumption, and implementing low latency error correction. Our approach toward achieving scalable feed-back based control systems includes the design of memory based arbitrary waveform generators (AWG’s), wide band radio frequency analog to digital converters, integrated amplifier chain, and state discriminators that can be synchronized with gate sequences. Digitally assisted designs, when implemented in an advanced CMOS node such as 7 nm can reap the benefits of low power due to scaling. A qubit readout chain demands several amplification stages before the digitizer. We propose the co-integration of our in-house developed InP HEMT LNAs with CMOS LNA stages to achieve the required gain at the digitizer input with minimal area. Our approach using high impedance matching between the HEMT LNA and the cryogenic CMOS receiver can relax the design constraints of an inverter-based CMOS LNA, paving the way toward a fully integrated qubit readout chain. The qubit state discriminator consists of a digital signal processor that computes the qubit state from the digitizer output and a pre-determined threshold. The proposed system realizes feedback-based optimal control for error mitigation and reduction of the required data rate through the serial interface to room temperature electronics.