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Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

29.3 A Cryo-CMOS Receiver with 15K Noise Temperature Achieving 9.8dB SNR in 10μs Integration Time for Spin Qubit Readout

Bagas Prabowo, Oriol Pietx-Casas, Mohammad Ali Montazerolghaem, Giordano Scappucci, Lieven M. K. Vandersypen, Fabio Sebastiano, Masoud Babaie

Published Feb 18, 2024• 19 citations
Publisher

Abstract

Continuous rounds of quantum error correction (QEC) are essential to achieve fault-tolerant quantum computers (QCs). In each QEC cycle, thousands of ancilla quantum bits (qubits) must be read out faster than the qubits’ decoherence time $(\gg \mathrm{T}_{2} * \sim 120 \mu \mathrm{s}$ for spin qubits). To address this urgent need, several CMOS receivers operating at cryogenic temperatures (cryo-CMOS RXs) have recently been introduced for gate-based [1] and RF reflectometry [2] readout of spin qubits, as well as transmons’ dispersive readout [3]. However, they have a few shortcomings. First, due to the temperature-independent shot noise of transistors in nanometer CMOS technology [4], their measured noise temperature $(\mathrm{T}_{{\mathrm {N}}})$ is limited to 40K, thus degrading qubit readout fidelity. Second, due to their large TN, prior art showed either only the electrical performance of their chips by applying a relatively large (i.e., -85dBm [2]) modulated signal directly to the RX input [2, 3] or offered limited qubit measurements by exploiting a HEMT amplifier prior to the RX [1]. Those issues hinder future monolithic integration between solid-state qubits and readout electronics. This work advances the prior art by (1) introducing a wideband passive amplification circuit at the RX front-end to minimize the shot noise contribution of the active devices, lowering prior art TNby $\sim 2.7\mathrm{x}$; (2) demonstrating the RX performance in an RF-reflectometry qubit readout scheme without using off-the-shelf LNA prior to the RX.

DOI
10.1109/isscc49657.2024.10454300

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Continuous rounds of quantum error correction (QEC) are essential to achieve fault-tolerant quantum computers (QCs). In each QEC cycle, thousands of ancilla quantum bits (qubits) must be read out faster than the qubits’ decoherence time (≫T2∗∼120μs(\gg \mathrm{T}_{2} * \sim 120 \mu \mathrm{s}(≫T2​∗∼120μs for spin qubits). To address this urgent need, several CMOS receivers operating at cryogenic temperatures (cryo-CMOS RXs) have recently been introduced for gate-based [1] and RF reflectometry [2] readout of spin qubits, as well as transmons’ dispersive readout [3]. However, they have a few shortcomings. First, due to the temperature-independent shot noise of transistors in nanometer CMOS technology [4], their measured noise temperature (TN)(\mathrm{T}_{{\mathrm {N}}})(TN​) is limited to 40K, thus degrading qubit readout fidelity. Second, due to their large TN, prior art showed either only the electrical performance of their chips by applying a relatively large (i.e., -85dBm [2]) modulated signal directly to the RX input [2, 3] or offered limited qubit measurements by exploiting a HEMT amplifier prior to the RX [1]. Those issues hinder future monolithic integration between solid-state qubits and readout electronics. This work advances the prior art by (1) introducing a wideband passive amplification circuit at the RX front-end to minimize the shot noise contribution of the active devices, lowering prior art TNby ∼2.7x\sim 2.7\mathrm{x}∼2.7x; (2) demonstrating the RX performance in an RF-reflectometry qubit readout scheme without using off-the-shelf LNA prior to the RX.
A scalable spin-qubit quantum processor requires fast, high-fidelity readout circuits operating at cryogenic temperatures (CTs). This work analyzes the radio frequency (RF) reflectometry readout mechanism to establish the link between conductance modulation, single-electron transistor (SET) matching network design, reflected signal power, and receiver (RX) noise temperature. Based on this analysis, a cryogenic RX architecture employing a passive switched-capacitor front-end is proposed. The front-end performs RF amplification and downconversion using transistors as switches, avoiding active RF amplification and mitigating shot-noise limitations. The RX is implemented in 40-nm CMOS and operates from 100 MHz to 2.2 GHz. Measurements demonstrate a minimum noise temperature of approximately 15 K at 4.2 K. When integrated with a quantum device, the RX achieves a signal-to-noise ratio (SNR) of 9.8 dB for a 10-µs integration time and enables 99.9% charge-state readout fidelity without external cryogenic amplifiers. This work represents the first demonstration of such fidelity using a cryo-CMOS RX and constitutes an important step toward scalable integration of qubit readout electronics.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at 3−4 K3-4 \mathrm{~K}3−4 K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of 10MHz−40MHz10 \mathrm{MHz}-40 \mathrm{MHz}10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at 3−4 K3-4 \mathrm{~K}3−4 K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be <1 mW\lt 1 \mathrm{~mW}<1 mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion, 4 K4 \mathrm{~K}4 K receiver for qubit readout that achieves >1.9GHz>1.9 \mathrm{GHz}>1.9GHz of IF bandwidth with >50 dB>50 \mathrm{~dB}>50 dB conversion gain and 0.7 dB0.7 \mathrm{~dB}0.7 dB NF while consuming only 17 mW17 \mathrm{~mW}17 mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing 3−5×3-5 \times3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.
In quantum computers, the quantum state discrimination of the physical quantum bits (Qubits) occupies ~80% of the quantum error correction (QEC) cycle. The RF reflectometry or dispersive readout determines the Qubit state by monitoring the RF reflection of the attached high-Q resonant tank. Compared to their dc counterparts, the RF reflectometers enjoy a high signal-to-noise ratio (SNR), low drifting, and fast speed. As a result, a high-fidelity, single-shot, scalable reflectometer array based on cryogenic CMOS (Cryo-CMOS) ICs is in demand for the future large-scale Qubit array (103∼10610^{3} {\sim } 10^{6}103∼106Qubits). However, the classic Cryo-CMOS heterodyne reflectometers, consisting of MOSFET-based LNA, mixer, and baseband blocks, suffer from high noise temperature and dc power. To address these issues, the Cryo-CMOS parametric circuitry based on varactors is explored. In this article, a dual-Qubit homodyne reflectometer array with 2 RX channels and 1 TX channel is demonstrated. In the RX, the degenerate parametric amplifier (DPA) enjoys a Q-enhanced,λRF/2\lambda _{\mathrm { RF}}/2λRF​/2differential-mode (DM) resonator for the high-gain parametric amplification. The common mode (CM) RF input of DPA interacts with the DM resonator by a nonreciprocal, dynamic mode coupling (DMC). It eliminates the necessity of a circulator and the potential oscillation of DPA. The scalability challenge of the DPA’s noise temperatureTnoiseT_{\mathrm { noise}}Tnoise​versus the environment temperatureTenvT_{\mathrm { env}}Tenv​is also investigated. In the TX, a current-mode logic (CML) divider with interstate locking and a vector modulator (VM) is implemented to achieve fast modulation for the spur and noise rejection. Measured at 4.2 K, the implemented 65 nm Cryo-CMOS chip presents a4.5∼74.5{\sim }74.5∼7GHz bandwidth, 52 dB peak RF gain, and 78 K noise temperature, and generates a 10 MHz TX pulse train with -22 dBm RF power and 30 dB tunability. It consumes a total dc power of 33 mW.
Spin qubits are a promising candidate for large-scale fault-tolerant quantum computing due to2footprint per qubit, higher operating temperature (up to 1K [1]) and possible compatibility with industrial CMOS processes [2], [3]. However, the need for a simultaneous ~µs readout of thousands of devices is especially challenging in terms of power consumption and footprint per qubit [4], [5]. Frequency-domain multiplexed (FDM) reflectometry architectures using cryo-CMOS have been introduced in [6], [7], [8] but these circuits require bulky > 100µm2inductors and do not match readout time specifications using actual quantum devices. Besides, current integrator readout schemes have been proposed [9], [10], but offer no scaling perspectives beyond time-domain multiplexing, leading to strong constraints in terms of bandwidth and power consumption. Recently, [4] introduced a capacitive-feedback transimpedance amplifier achieving an inductor-less FDM readout of two quantum dots [11]. Nevertheless, the demonstrated power consumption per qubit of 214µW/qubit remains too high to match the maximum heat dissipation allowed near quantum devices [12] in a large-scale perspective. Moreover, the used On-Off Keying (OOK) modulations are limited to one qubit per carrier, thus requiring high bandwidth and power consumption in order to read thousands of qubits.
Quantum computers (QCs) can perform certain computational problems exponentially faster than classical computers due to the superposition and entanglement properties of quantum bits (qubits). Among the various qubit technologies, superconducting qubits offer the fastest computational speed and are easy to fabricate, making them a strong candidate for large-scale QC systems with the potential to reduce both cost and complexity [1]. To execute practical quantum algorithms with real-time quantum error correction, thousands of qubits must be simultaneously controlled and read out much faster than the coherence time of the qubits (≪∼120μ s\ll \sim 120 \mu \mathrm{~s}≪∼120μ s). Current approaches require thousands of cables connecting the qubits to bulky room temperature (RT) equipment, which severely limits the scalability of control and readout electronics for QC systems with more than 10310^{3}103 qubits. To address this issue, the electronic interfaces must be placed in close proximity to the qubits, or ideally co-integrated and operated at similar cryogenic temperatures (CTs) with the qubits [1, 2]. This work proposes a 4 -to7 GHz single-chip fully integrated readout integrated circuit (ROIC) with 48 K noise temperature measured at 26 K,253MHzIF26 \mathrm{~K}, 253 \mathrm{MHz} \mathrm{IF}26 K,253MHzIF bandwidth (BW), and 52.3 dB spurious-free dynamic range (SFDR) for compatibility with superconducting multi-qubits read-out.
A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3digitally controlled oscillator required to manipulate the state of qubits.