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IEEE Asian Solid-State Circuits Conference (A-SSCC)

A 4-to-7GHz, 52.3dB SFDR, and 48K Noise Temperature Cryo-CMOS based Noise-Canceling Receiver for Superconducting Multi-Qubits Read-Out

Hyeonsik Ahn, Juhui Jeong, Putri Assyifa Nur Annisa Rizk, Junhyeop Kim, Jae-Won Nam, Jusung Kim, Junghwan Han

Published Nov 2, 2025• 1 citation
Publisher

Abstract

Quantum computers (QCs) can perform certain computational problems exponentially faster than classical computers due to the superposition and entanglement properties of quantum bits (qubits). Among the various qubit technologies, superconducting qubits offer the fastest computational speed and are easy to fabricate, making them a strong candidate for large-scale QC systems with the potential to reduce both cost and complexity [1]. To execute practical quantum algorithms with real-time quantum error correction, thousands of qubits must be simultaneously controlled and read out much faster than the coherence time of the qubits ($\ll \sim 120 \mu \mathrm{~s}$). Current approaches require thousands of cables connecting the qubits to bulky room temperature (RT) equipment, which severely limits the scalability of control and readout electronics for QC systems with more than $10^{3}$ qubits. To address this issue, the electronic interfaces must be placed in close proximity to the qubits, or ideally co-integrated and operated at similar cryogenic temperatures (CTs) with the qubits [1, 2]. This work proposes a 4 -to7 GHz single-chip fully integrated readout integrated circuit (ROIC) with 48 K noise temperature measured at $26 \mathrm{~K}, 253 \mathrm{MHz} \mathrm{IF}$ bandwidth (BW), and 52.3 dB spurious-free dynamic range (SFDR) for compatibility with superconducting multi-qubits read-out.

DOI
10.1109/a-sscc67472.2025.11349425

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Quantum computing holds the promise to solve problems that are currently intractable by classical computing platforms. Such computing framework relies on the properties of quantum bits (qubits) that operates at cryogenic temperatures well below 1K. Besides a quantum processor, an operational quantum computer needs a classical electronic controller reading out the electrical signals generated by the qubits and the providing electrical control to perform the required operations on the qubits. Since today’s quantum processors comprise a low number of qubits (<10), most controlling electronics can operate at room temperature and be connected by bulky interconnects to the cryogenic qubit chamber. However, when scaling up to the thousands of qubits required in a practical quantum algorithm, the classical electronics must be placed at cryogenic temperature to simplify the interconnects and allow a compact, reliable and scalable system. In this work, we propose the fully-integrated implementation in standard CMOS technology of the electronic read-out for spin qubits. Simulations show that the proposed current read-out circuit can achieve a 10MHz bandwidth that is 10X wider than current state-of-the-art read-outs while keeping comparable noise performance and operating at 4.2K. Such results are a promising indication that cryogenic CMOS circuits can provide the building blocks for the integration of the classical electronic controller for future scalable quantum computers.
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